The module cmac_usplus_0_pkt_mon is responsible for reception of packets. Typically the packet monitor waits for transceivers to achieve lock and for the 100G Ethernet IP RX to align. After this has occurred, the packet monitor receives a predefined number of packets. The FSM is used to monitor the RX LBUS signals. A functional description of each state follows:
• STATE_RX_IDLE : By default, the FSM is in the IDLE state. When reset_done goes High, the FSM moves to the STATE_GT_LOCKED state.
• STATE_GT_LOCKED : This state sets gt_lock_led =1, rx_core_busy_led =1, and ctl_rx_enable =1. Then the FSM moves to the STATE_WAIT_RX_ALIGNED state.
• STATE_WAIT_RX_ALIGNED : This state waits for stat_rx_aligned =1, which indicates that the 100G Ethernet IP RX core is aligned. The FSM then moves to the STATE_PKT_TRANSFER_INIT state.
• STATE_PKT_TRANSFER_INIT : This state sets rx_aligned_led =1, rx_core_busy_led =1, initializes all signals to start LBUS packet generation, and then moves to the STATE_LBUS_TX_ENABLE state.
• STATE_LBUS_RX_ENABLE : This state receives LBUS packets and compares them to the expected packets. If there is a mismatch, it sets rx_data_fail_led =1. This flag is reset only when lbus_tx_rx_restart_in =1. After receiving all the packets, the FSM moves to the STATE_LBUS_RX_DONE state.
• STATE_LBUS_RX_DONE : This state resets all the signals related to LBUS packets, sets the rx_done_led =1, and moves to the STATE_WAIT_FOR_RESTART state. If the TX Flow Control and RX Flow Control functions are enabled, it waits for pause_test_done =1 and then moves to the STATE_WAIT_FOR_RESTART state. If 1588 1-step is enabled, then the FSM moves to the STATE_RX_PTP_ENABLE state.
• STATE_RX_PTP_ENABLE : In this state, it receives the three 1588 PTP packets. After receiving the packets, the FSM moves to the STATE_RX_PTP_DONE state.
• STATE_RX_PTP_DONE : This state is only to display the time stamps received. If the TX Flow Control and RX Flow Control are enabled, wait for the pause_test_done =1 and move to STATE_WAIT_FOR_RESTART state.
• STATE_WAIT_FOR_RESTART : This state resets all signals related to the LBUS packet monitor and resets rx_core_busy_led =0. It then waits for rx_restart_rise_edge =1 and stat_rx_aligned =1. The FSM then moves to the STATE_PKT_TRANSFER_INIT state.
If any time stat_rx_aligned = 0, then the FSM moves to STATE_RX_IDLE state.
• When RX_FLOW_CONTROL is enabled, the corresponding input control signals will be initialized to enable Pause and Priority Pause frames reception.
• If you select Disable FCS Stripping in the General tab, the CRC_Mapping_LUT module will be instantiated inside the cmac_usplus_0_pkt_mon module. This CRC_Mapping_LUT module contains the pre-calculated CRC values for the received LBUS data packets of packet size 522 bytes. These CRC values will be compared with the received LBUS packet CRC.
• If you change the packet size, you must provide the new CRC values as appropriate for the new packet size.
The state transition occurring during this process is shown in This Figure .