Pause Processing Interface - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The dedicated 100G Ethernet IP core provides a comprehensive mechanism for pause packet termination and generation. The TX and RX have independent interfaces for processing pause information as described in this section.