Product Specification - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2023-05-24
Version
3.1 English

Table: Integrated CMAC Block for the 100 Gb/s Ethernet Solution defines the integrated CMAC block for the 100 Gb/s Ethernet solution.

Table 2-1: Integrated CMAC Block for the 100 Gb/s Ethernet Solution

Protocol

Lane Width

Line Rate

SerDes

SerDes Width

CAUI-10

x10

10.3125 Gb/s

GTH

GTY

32b

CAUI-4

x4

25.78125 Gb/s (2)

GTY (1)

GTM

With GTY: 80b

With GTM: 64b

Runtime Switchable CAUI-4/CAUI-10

CAUI-10: x10

CAUI-4: x4

CAUI-10: 10.3125 Gb/s

CAUI-4: 25.78125 Gb/s

GTY (1)

CAUI-10: 32b

CAUI-4: 80b

100GAUI-2

x2

53.125 Gb/s (3)

GTM

160b

100GAUI-4

x4

26.5625 Gb/s

GTY (4)

GTM

With GTY: 80b

With GTM: 64b

Notes:

1. CAUI-4 requires GTY or GTM transceivers which are available in select devices. Runtime switchable CAU-10/CAUI-4 require GTY transceivers available only in select devices.

2. The line rate of 25.78125 Gb/s is available on select devices in typical speed grades.

3. The line rate of 53.125 Gb/s (GTM transceivers) is available on select devices.

4. 100GAUI-4 requires GTY or GTM transceivers which are available in select devices.

The core instantiates the CMAC block along with the necessary GTH, GTY, or GTM transceivers. The core provides an example of how the two blocks are connected together, along with the reset and clocking for those blocks.

The integrated block is designed to IEEE std 802.3-2012 [Ref 2] .

This Figure illustrates the following interfaces to the integrated CMAC block.

Serial transceiver interface

User-side transmit and receive LBUS or AXIS interface

Pause processing

IEEE 1588-2008 [Ref 1] timestamping interface

Status/Control interface

DRP interface used for configuration

RS-FEC IP Block

Figure 2-1: Integrated CMAC Block for 100 Gb/s Ethernet

X-Ref Target - Figure 2-1

X17785-cmac-block.jpg