RS Decoding - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The signals rsfec_bypass_rx_din_cw_start , rsfec_bypass_rx_dout_cw_start and rsfec_bypass_rx_dout_valid behave in an analogous manner to the corresponding TX signals. 16 cycles of data with 330 bits per cycle transfers one 5280-bit codeword input (including received parity symbols). On the 17th cycle, the decoder is ready to accept another pulse on rsfec_bypass_rx_din_cw_start and begin processing the next codeword.

The rsfec_bypass_rx_dout_valid is only asserted when rsfec_bypass_rx_dout_cw_start has been asserted and the corresponding data is present on the output. If rsfec_bypass_rx_din_cw_start is reasserted before the last cycle of the codeword has been presented on the input bus, rsfec_bypass_rx_dout_valid is deasserted to indicate that the output data is no longer valid. rsfec_bypass_rx_dout_valid is reasserted when the data corresponding to a new rsfec_bypass_rx_din_cw_start is present on the output.