RX GT/Lane Logic Clock (RX_SERDES_CLK) - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

These clocks are provided to the CMAC block from the serial transceiver (GT) to clock the Lane Logic RX interface. The clocks must be 322.266 MHz for CAUI-10, CAUI-4, 100GAUI-4, and 100GAUI-2 operation. The GT interface datapath is 32 bits per lane for CAUI-10, 80 bits per lane for CAUI-4/100GAUI-4, and 160 bits per lane for 100GAUI-2.

The other implementation allows only one RX_SERDES_CLK to go to the Ethernet MAC RX_SERDES_CLK inputs. The serial transceiver will also be in raw mode but this time the buffer is used. This mode is used when you can tolerate higher latency and are interested in saving FPGA clocking resources.