RX OTN Interface - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

After the received data is aligned and reordered, the BIP8 value for the 66b words is calculated and both are output through the OTN interface. The RX OTN block handles the translation of the received data to the desired format and clock domain of the OTN interface. If the OTN and RX core clocks are different, a FIFO-based clock domain crossing bridge is used; otherwise, a simple pipeline is used.

The OTN Interface will have OTN_LANES == 5 lanes of data, and will be locked to the rx_clk of the hard IP. This implementation also makes use of the existing statistics interface of the RX MAC+PCS block.

The Integrated 100G Ethernet can be configured with an optional 802.3bj-2014 RSFEC block on the input datapath. When so configured, the OTN IP interface will take data after the RSFEC and thus gain any error correction afforded by this block.

The output enable pattern for the OTN interface has one single cycle where rx_otn_ena is '0' for every 33 rx_otn_clk cycles (32 cycles rx_otn_ena == 1'b1, followed by one cycle rx_otn_ena == 1'b0).

The RX OTN interface is always active.