Receive Timestamp Function - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The ingress logic does not parse the ingress packets to search for 1588 (PTP) frames. Instead, it takes a timestamp for every received frame and outputs this value to the user logic. The feature is always enabled, but the timestamp output can be ignored if this function is not required.

See Table: Transceiver I/O for a detailed description of signals related to the RX timestamping function.

To compensate for lane skew, the alignment buffer fill levels for each PCS lane are provided as outputs. The RX timestamp function is shown in This Figure .

Figure 3-18: RX Timestamping

X-Ref Target - Figure 3-18

pg165_1588v2__rx_timestamp_capture_x14342.jpg

In This Figure , timestamps are captured for each word of lane 0 which is exiting the gearbox plane. The capture logic accounts for the gearbox dead cycle which occurs every 33 cycles.

IMPORTANT: The RX system timer input must be in lane 0 of the RX SerDes clock domain.

Timestamps are filtered after the PCS decoder to retain only those timestamps corresponding to an SOP. The PCS also identifies the PCS lane on which the SOP occurred.

The lane alignment fill buffers are carried through to the user interface output. These average values of the fill levels are not expected to vary over time. The average value should be taken to the required accuracy to remove the clock cycle jitter. The alignment fill values reflect the static skew present in each lane.

The signals stat_rx_pcsl_number_0[4:0] to stat_rx_pcsl_number_19[4:0] can be used to correlate each PCS lane to a physical lane.

Soft logic improves timestamp accuracy and compensate for the lane alignment FIFO fill levels by adding or subtracting the relative fill level of the selected lane. The reference fill level is the average fill level of the rx lane aligner fill after the PCS lane number carried by rx_ptp_pcslane_out is translated to a PMD lane number via the stat_rx_pcsl_number_* . The relationship between the 100G Ethernet IP core and the soft logic is shown in This Figure .

Figure 3-19: Soft Logic

X-Ref Target - Figure 3-19

pg165_example_soft_logic_x14343.jpg

The corrected timestamp is computed as:

rx_ptp_tstamp_out + (Reference Fill Level - rx_lane_aligner_fill_0 )

Where:

rx_ptp_tstamp_out is the timestamp at the first gearbox, and is filtered by the PCS to correspond to the start of the SOP. The rx_ptp_tstamp_out value is a unit of time, whereas the fill level is not a unit of time. To translate the fill level to time, multiply the fill level by the cycle period.

rx_lane_aligner_fill_0 is the time average of the alignment buffer fill level for the lane on which the timestamp was taken.

Reference fill level is the average fill level of the rx lane aligner fill after the PCS lane number carried by rx_ptp_pcslane_out is translated to a PMD lane number through the stat_rx_pcsl_number_* .