Revision History - 3.1 English

11/02/2022

3.1

Updated the Simulation Speed Up section.

02/04/2021

3.1

Chapter 5: Example Design

• Updates to RESET_REG and Status and Statistics Register Map .

Appendix D: Auto-Negotiation and Link Training

• Updated Validation Steps for Auto Negotiation and Link Training with AXI4-Lite Interface .

06/24/2020

3.1

General updates

• Added 100GAUI-4 support.

Chapter 5: Example Design

• New details added about RS-FEC Simulation in RS-FEC Enabled Configuration Simulation .

• Updates to CORE XCI Top Level Port List .

Appendix G: Debugging

• Added new section detailing Debugging Auto-Negotiation and Link Training .

10/30/2019

3.0

Chapter 4: Design Flow Steps

• Updated figures.

Chapter 5: Example Design

• Updated This Figure .

Appendix A: UltraScale+ Device RS-FEC for Integrated 100G Ethernet

• Updated Table: Common Ports .

Appendix D: Auto Negotiation and Link Training

• Added new section Validation Steps for Auto Negotiation and Link Training with AXI4-Lite Interface .

05/22/2019

2.6

Chapter 1: Overview

• Updated Table: Licensing Details .

Chapter 2: Product Specification

• Added AXI4-Stream interface to bullet.

• Added AXI4-Stream description in Typical Operation .

Chapter 3: Designing with the Core

• Added 100GAUI-2 throughout chapter.

• Added Table: Supported CMAC-GTM configurations .

• Updated GT Interface Width for 100G (4 x 25.78125) in Table: 100G PCS Frequencies .

• Updated This Figure and This Figure .

• Updated This Figure and This Figure .

• Added User Side AXI4-Stream Interface section.

Chapter 4: Design Flow Steps

• Updated figures.

• Added AXIS and Include Statistics Counters and Statistics Resource Type parameters in Table: General Tab .

Chapter 5: Example Design

• Added AXI4-Stream TX and RX in Table: CORE XCI Top Level Port List .

• Added table note in Table: Status and Statistics Register Map .

• Added Bits[15:11] in Table: CONFIGURATION_AN_ABILITY .

• Updated Bits[13, 6] Type in Table: STAT_AN_STATUS_REG .

• Updated Bits[19:11] in Table: STAT_AN_ABILITY_REG .

• Updated Bits[31:22] in Table: STAT_AN_LINK_CTL_REG_1 .

• Added new register Table: STAT_AN_LINK_CTL_REG_2 .

• Updated code in Core Bring Up Sequence .

Appendix D: Auto Negotiation and Link Training

• Updated Bits[5:0] description in Table: Status Report Field Bit Definitions .

12/05/2018

2.5

IP Facts

• Added Optional soft TX OTN interface bullet in Features .

Chapter 1: Overview

• Added 100GAUI-2 note and GTM in Overview .

Chapter 2: Product Specification

• Updated Table: Integrated CMAC Block for the 100 Gb/s Ethernet Solution .

• Added GTM in Product Specification .

• Updated This Figure .

• Updated important note in Port Descriptions .

Chapter 3: Designing with the Core

• Added CMAC with GTM Mapping .

• Updated This Figure to This Figure .

• Added GTM throughout.

• Added This Figure to This Figure .

• Added AR71785 note after This Figure .

• Updated Transceiver Selection Rules .

Chapter 4: Design Flow Steps

• Updated figures.

• Updated Table: General Tab and Table: GT Selections and Configuration Tab .

Chapter 5: Example Design

• Updated gt_rxusrclk2 and added user_reg0 in Table: CORE XCI Top Level Port List .

• Added USER_REG0 in Table: Configuration Register Map .

• Added Table: USER_REG0 .

Appendix A: UltraScale+ Device RS-FEC for Integrated 100G Ethernet

• Added codeword description in Statistics and Codeword Flags .

Appendix B: UltraScale+ Device RX OTN Interface

• Updated This Figure .

Appendix C: UltraScale+ Device TX OTN Interface

Added note in first paragraph in Soft TX OTN Interface .

04/04/2018

2.4

• Updated descriptions for STAT_RX_PCSL_NUMBER_0[4:0] to STAT_RX_PCSL_NUMBER_19[4:0] throughout.

Chapter 5: Example Design

• Added the gt_txpippmen, gt_txpippmsel, and stat_reg_compare_out ports.

• Defined the .h Header File.

• Updated register names:

° STAT_RX_PCSL_DEMUXED to STAT_RX_PCSL_DEMUXED_REG

° STAT_RSFEC_STATUS to STAT_RSFEC_STATUS_REG

° STAT_RSFEC_LANE_MAPPING to STAT_RSFEC_LANE_MAPPING_REG

° STAT_AN_STATUS to STAT_AN_STATUS_REG

° STAT_AN_LINK_CTL to STAT_AN_LINK_CTL_REG

° STAT_AN_ABILITY to STAT_AN_ABILITY_REG

• Added STAT_TX_OTN_RSFEC_STATUS_REG register.

• Added 0x0258 to 0x0278 address, and removed 0x0758 to 0x0778.

10/04/2017

2.4

Chapter 5: Example Design

• Updated the port s_axi_pm_tick to pm_tick.

• Updated the port description for rx_serdes_clk.

• Added the port send_continuous_pkts.

• Updated the “Configuration Register Map” table and the “Status and Statistices Register Map” table with new registers & addresses.

• Updated the Core Bring Up Sequence section.

Appendix A: Auto-Negotiation and Link Training

• Updated the port ctl_an_cl91_ability to ctl_an_cl91_fec_ability.

06/07/2017

2.3

• Changed signal names stat_rx_vl_* to stat_rx_pcsl_* throughout.

Chapter 3: Designing with the Core

• Added Frame-by-Frame Timestamping Operation section.

Chapter 5: Example Design

• Added the gt_powergoodout, gt_ref_clk_out, tx_preamblein, rx_preambleout and ctl_rsfec_enable signals.

• Updated the Configuration Register Map table.

• Added the following Status and Statistics Register Map addresses: 0x023C, 0x0718, 0x0720, 0x0728, 0x0730, 0x0738, 0x0740, 0x0748, 0x0750, 0x103C.

• Added the following Register Description tables: CONFIGURATION_TX_OTN_PKT_LEN_REG, CONFIGURATION_TX_OTN_CTL_REG, CONFIGURATION_TX_OTN_PKT_LEN_REG, CONFIGURATION_TX_OTN_CTL_REG, STAT_TX_OTN_STATUS_REG, STAT_TX_OTN_RSFEC_STATUS_REG

04/05/2017

2.2

• Added a new appendix for the soft TX OTN interface.

• Added a new appendix for the auto-negotiation and link training features.

11/30/2016

2.1

Chapter 2: Overview

• Removed device restriction in important note, because all UltraScale+® devices have CAUI-10/CAUI-4.

Chapter 2: Product Specification

• Updated the TX_RDYOUT port description.

• Updated bus values for STAT_RX_FRAMING_ERR_ N , STAT_RX_BAD_FCS, STAT_RX_STOMPED_FCS, STAT_RX_UNDERSIZE, STAT_RX_FRAGMENT, and STAT_RX_BAD_CODE, STAT_RX_TOTAL_BYTES, STAT_RX_TOTAL_PACKET, STAT_RX_PACKET_SMALL .

Chapter 3: Designing with the Core

• Added addition CAUI-4 rule in Transceiver Selection Rules.

Chapter 4: Design Flow Steps

• Updated the Vivado IP catalog tab screen captures.

• General tab: Added the TX IPG Value parameter.

Chapter 5: Example Design

• Changed the axi_gt_loopback port name to ctl_gt_loopback.

• Updated the drp_addr port description.

• Added the stat_rx_rsfec_hi_ser, stat_rx_rsfec_lane_alignment_status, and stat_rx_rsfec_lane_mapping signals.

10/05/2016

2.0

Chapter 2: Product Specification

• Updated the Clock Domain for CTL_RX_SYSTEMTIMERIN[80-1:0].

• Updated the Default Value for CTL_RX_OPCODE_PPP[15:0] and CTL_TX_OPCODE_PPP[15:0].

Chapter 3: Designing with the Core

• Added further details about Synchronous Mode and Asynchronous Mode in the Resets section.

Chapter 4: Design Flow Steps

• Changed GT Selections and Configuration tab to CMAC / GT Selections and Configuration tab throughout.

Chapter 5: Example Design

• Added new Example Design Hierarchy (GT Subcore in Example Design) section, and diagram.

• Added the tx_clk, gtwiz_userdata_tx_in, gtwiz_userdata_rx_out, txdata_in, txctrl0_in, txctrl1_in, rxdata_out, rxctrl0_out, rxctrl1_out, gt_txinhibit, axi_gt_reset_all, and axi_gt_loopback signals.

• Updated the Configuration Register Map table.

• Added the GT_LOOPBACK_REF table.

• Added Simulation Speed Up section.

04/06/2016

1.0

Initial Xilinx Release.