STAT_RX_MF_LEN_ERR[19:0] - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

When a bit of this bus is 1, it indicates that PCS Lane Marker Words are being received but not at the expected rate in the corresponding lane. The transmitter and receiver must be re-configured with the same Meta Frame length.

The bits of the bus remain asserted until word boundary synchronization occurs or until some other error/failure is signaled for the corresponding lane.