STAT_RX_PCSL_NUMBER_[0-19][4:0] - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

Each bus indicates which PCS lane will have its status reflected on a specific status pins. For example, STAT_RX_PCSL_NUMBER_0 indicates which PCS lane will have its status reflected on pin 0 of the other status signals. These buses can be used to detect if a PCS lane has not been found or if one has been mapped to multiple status pins.

In CAUI-10 mode:

The physical lanes 0, 1 map to GT0,

The physical lanes 2, 3 map to GT1,

The physical lanes 4, 5 corresponds to GT2, and so forth.

In CAUI-4 mode:

The physical lanes 0, 1, 2, 3, 4 map to GT0,

The physical lanes 5, 6, 7, 8, 9 map to GT1,

The physical lanes 10, 11, 12, 13, 14 map to GT2, and

The physical lanes 15, 16, 17, 18, 19 map to GT3.