Shared Logic Implementation - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

Shared logic includes the GT common module which can be present as part of GT or in the example design. By default, shared logic is present inside the core. If you want to instantiate shared logic in the example design, select Include Shared logic in example design in the Vivado IDE.

This Figure shows the implementation when shared logic is instantiated in the example design.

Figure 5-11: Example Design Hierarchy with Shared Logic Implementation (GT Subcore in Core)

X-Ref Target - Figure 5-11

X16360-pg203-example-design-hier-shared-logic.jpg