Simulation Speed Up - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

Simulation can take a long time to complete due to the time required to complete alignment. A `define SIM_SPEED_UP is available to improve simulation time by reducing the PCS lane Alignment Marker (AM) spacing in order to speed up the time the IP will take to achieve alignment. Setting `define SIM_SPEED_UP will change CTL_TX_VL_LENGTH_MINUS1 and CTL_RX_VL_LENGTH_MINUS1 from 16'h3FFF to 16'h03FF.

The SIM_SPEED_UP option can be used for simulation when in serial loopback or if the Alignment Marker spacing can be reduced at both endpoints. This option is compatible with the example design simulation which uses serial loopback.