Slow Simulation - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

Simulations can appear to run slowly under some circumstances. If a simulation is unacceptably slow, the following suggestions can improve the run-time performance.

Use a faster computer with more memory.

Make use of a Platform LSF (Load Sharing Facility), if available.

Bypass the Xilinx transceiver (this might require creating your own test bench).

Send fewer packets. This can be accomplished by modifying the appropriate parameter in the provided sample test bench.

Specify a shorter time between alignment markers. This should result in a shorter lane alignment phase at the expense of more overhead. However, when the 100G Ethernet IP core is implemented in hardware, the distance between alignment markers should follow the specification recommendations (after every 16,383 word). For more information, see Simulation Speed Up .