Soft TX OTN Interface - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The soft TX OTN logic implemented in fabric logic can be optionally selected in the wizard when you configure the CMAC. Optionally, soft TX RS-FEC can be included in the soft TX OTN Interface.

Note: The soft RS-FEC LogiCORE™ is a fee-based licensed IP. For more information on ordering and RS-FEC details, see the 100G RS-FEC product web page.

The soft TX OTN block handles the translation of the OTN data to the desired format and clock domain. If the OTN and SerDes are on different clock domains, a FIFO-based clock domain crossing bridge is used; otherwise, a simple pipeline is present. The BIP8 information along with the alignment markers are transparently passed by the IP on the TX.

For implementations where a full MAC+PCS is present, the OTN data is sent to the gearbox block based on the tx_otn_ena port. The RX OTN interface is always active.

Figure C-1: Block Diagram of the Integrated CMAC With Optional Soft TX OTN Interface

X-Ref Target - Figure C-1

X18919-block-diagram-tx-otn.jpg