Soft TX OTN Interface Bus Timing - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

This Figure illustrates the bus timing for the OTN interface on the integrated CMAC where OTN_LANES is equal to 5, and TX OTN ports are present.

Figure C-2: Bus Timing for the OTN Interface

X-Ref Target - Figure C-2

X17365-otn-interface-bus-timing.jpg

The five lanes of data are qualified by the tx_otn_ena enable bus, and are only ready when the enable is 1. The gearbox logic within the CAUI block requires two cycles of ena 0 in every 66 cycles. To ensure gearbox synchronization, a tx_otn_stall signal is provided to guide the user logic TX enable.

The user should assert tx_otn_lane0_sync when tx_otn_data0 contains PCS Lane 0s data on the TX interface.

In this example, the Alignment Markers is present on the OTN interface for four cycles of data, indicated by the tx_otn_vlmarker .