Stages and Status Signals - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

1. At the start of AN, there is a TX disable state where no data is seen to ensure that the link is down on both sides. The stat_an_start_tx_disable signal toggles for one cycle to indicate the start of this stage.

2. Following the TX disable state, AN information is exchanged. During this stage, stat_an_rxcdrhold is held High. The stat_an_lp_autoneg_able and stat_an_lp_ability_valid signals toggle High for one clock cycle to indicate when stat_an_lp* information is valid.

3. The stat_an_start_an_good_check signal toggles High for one cycle at the start of link training. The stat_an_rxcdrhold signal is deasserted, and gtwiz_reset_rx_datapath toggled.

4. After link training starts, there is a 500 ms timer to allow training and block lock, link up in mission mode, and normal PCS operation to complete, or AN will restart. The stat_lt_frame_lock signal goes High and the stat_lt_rx_sof signal toggles when the link training block has achieved frame synchronization. The stat_lt_rx_sof signal continues to toggle High for one clock cycle at the training frame boundary.

5. When link training completes, the stat_lt_signal_detect signal is asserted. This indicates the start of normal PCS operation.

6. The an_autoneg_complete signal goes High when block lock, synchronization, and (in the case of the multi-lane core) alignment are complete. The stat_rx_status and stat_rx_valid_ctrl_code signals go High.

Note: The stat_rx_valid_ctrl_code signal is only applicable to the single-lane 10G/25G core.

7. The an_autoneg_complete signal must go High within the 500 ms timeout,. If this does not happen, AN restarts. If the stat_rx_status signal goes back to Low at any time, AN restarts.