Sub-Mode 4: Correction, No Indication - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

In this sub-mode, the RS-FEC engine detects and corrects errors.

If a codeword with up to 7 symbol errors is received, the errors are corrected and the data is passed to the Integrated 100G Ethernet.

If a codeword with 8 or more symbol errors is received, the erroneous data is also passed to the Integrated 100G Ethernet with no indication that it is incorrect.

To reduce the chance that errors in a packet are undetected, the RS-FEC engine performs additional error monitoring in this mode. The number of symbol errors seen is accumulated over consecutive non-overlapping windows of input codewords. If the symbol error count within any window exceeds a fixed threshold, the RS-FEC engine sets its hi_ser flag to true and causes the data being passed to the Integrated 100G Ethernet to have all of its 2-bit synchronization headers corrupted for a long period (>60 ms). This causes the Integrated 100G Ethernet to set its hi_ber flag to true, inhibiting the processing of received packets.

The primary purpose of the different sub-modes is to allow latency to be reduced in cases where the line BER is low enough that full error correction is not required. The latency of the RS-FEC engine in each available operating mode is shown in Table: RS-FEC Engine Latency .

Table A-4: RS-FEC Engine Latency

Receive sub-mode

Normal mode latency

Transcode bypass mode latency

Clock cycles

Nanoseconds

Clock cycles

Nanoseconds

1

37

114.8

27

83.8

2

24

74.5

14

43.4

3

12

37.2

2

6.2

4

37

114.8

27

83.8

Transmit

7

21.7

4

12.4