TX CLK - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

This clock is provided to both the CMAC block and serial transceiver to clock the GT/ lane logic TX interface as well as the whole Ethernet MAC. The clock must be 322.266 MHz for CAUI-10, CAUI-4, 100GAUI-4, and 100GAUI-2 operation. The GT lane logic interface datapath is 32 bits per lane for CAUI-10 and 80 bits per lane for CAUI-4, 100GAUI-4, and 100GAUI-2. Only one TX_CLK is needed regardless of CAUI-10/CAUI-4/100GAUI-4/100GAUI-2 implementation. This clock also clocks the transmit Ethernet MAC, LBUS/AXIS interface, and the Control/Status port.