TX LBUS Interface - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The synchronous TX Local bus interface accepts packet-oriented data of arbitrary length. All signals are synchronous relative to the rising-edge of the clk port. This Figure shows a sample waveform for data transactions for two consecutive 65-byte packets using a 512-bit segmented bus. Each of the four segments is 128 bits wide.

Figure 3-14: Transmit Timing Diagram

X-Ref Target - Figure 3-14

pg165_cmac_seg_lbus_transmit_x14326.jpg