TX Pause Generation - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

You can request a pause packet to be transmitted using the CTL_TX_PAUSE_REQ[8:0] and CTL_TX_PAUSE_ENABLE[8:0] input buses. Bit 8 corresponds to global pause packets and bits [7:0] correspond to priority pause packets.

Each bit of this bus must be held at a steady state for a minimum of 16 cycles before the next transition.

IMPORTANT: The 100G Ethernet IP core does not support assertion of global and priority pause packets at the same time.

The contents of the pause packet are determined using the following attributes.

Global pause packets:

CTL_TX_DA_GPP[47:0]

CTL_TX_SA_GPP[47:0]

CTL_TX_ETHERTYPE_GPP[15:0]

CTL_TX_OPCODE_GPP[15:0]

CTL_TX_PAUSE_QUANTA8[15:0]

Priority pause packets:

CTL_TX_DA_PPP[47:0]

CTL_TX_SA_PPP[47:0]

CTL_TX_ETHERTYPE_PPP[15:0]

CTL_TX_OPCODE_PPP[15:0]

CTL_TX_PAUSE_QUANTA0[15:0]

CTL_TX_PAUSE_QUANTA1[15:0]

CTL_TX_PAUSE_QUANTA2[15:0]

CTL_TX_PAUSE_QUANTA3[15:0]

CTL_TX_PAUSE_QUANTA4[15:0]

CTL_TX_PAUSE_QUANTA5[15:0]

CTL_TX_PAUSE_QUANTA6[15:0]

CTL_TX_PAUSE_QUANTA7[15:0]

The dedicated 100G Ethernet IP core automatically calculates and adds the FCS to the packet. For priority pause packets, the dedicated 100G Ethernet IP core also automatically generates the enable vector based on the priorities that are requested.

To request a pause packet, you must set the corresponding bit of the CTL_TX_PAUSE_REQ[8:0] and CTL_TX_PAUSE_ENABLE[8:0] bus to a 1 and keep it at 1 for the duration of the pause request (that is, if these inputs are set to 0, all pending pause packets are canceled. Pause is canceled by sending out additional pause packet with pause quanta set to 0).

The dedicated 100G Ethernet IP core will transmit the pause packet immediately after the current packet in flight is completed. Each bit of this bus must be held at a steady state for a minimum of 16 cycles before the next transition.

To retransmit pause packets, the dedicated 100G Ethernet IP core maintains a total of nine independent timers: one for each priority and one for global pause. These timers are loaded with the value of the corresponding input buses. After a pause packet is transmitted the corresponding timer is loaded with the corresponding value of the CTL_TX_PAUSE_REFRESH_TIMERn[15:0] input bus ( n ranges from 0 to 8). When a timer times out, another packet for that priority (or global) is transmitted as soon as the current packet in flight is completed. Additionally, you can manually force the timers to 0, and therefore, force a retransmission by setting the CTL_TX_RESEND_PAUSE input to 1 for one clock cycle.

To reduce the number of pause packets for priority mode operation, a timer is considered "timed out" if any of the other timers time out. Additionally, while waiting for the current packet in flight to be completed, a new timer that times out or any new request from the user will be merged into a single pause frame. For example, if two timers are counting down, and you send a request for a third priority, the two timers are forced to be timed out and a pause packet for all three priorities is sent as soon as the current in-flight packet (if any) is transmitted.

Similarly, if one of the two timers times out without an additional user request, both timers are forced to be timed out and a pause packet for both priorities is sent as soon as the current in-flight packet (if any) is transmitted.

You can stop pause packet generation by setting the appropriate bits of CTL_TX_PAUSE_REQ[8:0] or CTL_TX_PAUSE_ENABLE[8:0] to 0.