The design must meet the following rules when connecting the 100G Ethernet IP core to the transceivers.
If implementing CAUI-10:
•CAUI-10 GTs have to be contiguous.
•CAUI-10 must include two or four GTs from the quad in the same horizontal Clock Region (CR) as the 100G Ethernet IP.
•CAUI-10 must be implemented within an SLR.
•CAUI-10 mode GT RX Buffer Bypass configuration cannot be enabled with GTY from column across the device.
If implementing CAUI-4/100GAUI-4:
•CAUI-4/100GAUI-4 GTs have to be contiguous.
•CAUI-4/100GAUI-4 must use GTYs from the same horizontal CR or two above or below.
•CAUI-4/100GAUI-4 all GTs must come from the same GT quad (for GTY).
•CAUI-4/100GAUI-4 is only supported in Lanes 1-4.
•For 100GAUI-4/CAUI-4 with GTM configuration, two GTM duals (each GTM dual has two GT channels) are used. The GTM duals should be from the same horizontal CR or one above or below.
•CAUI-4/100GAUI-4 must be implemented within an SLR.
•To use RX Buffer Bypass, CAUI-4 must use the same CR or two above or below. GT RX Buffer Bypass cannot be enabled with the GTY from the column across the device.
If implementing 100GAUI-2:
•For 100GAUI-2 configuration, one GTM dual is used.
•100GAUI-2 must use GTM duals from the same horizontal CR or one above or below.
•100GAUI-2 GT channels must be from the same GTM dual.
•100GAUI-2 must be implemented within an SLR.
If implementing Runtime Switchable CAUI-10/CAUI-4, follow the preceding rules for both CAUI-10 and CAUI-4 rules.
IMPORTANT: For Runtime Switchable mode, if the GT group is selected as two GTs from bottom quad, four GTs from middle and four GTs from upper quad, then when it switches from CAUI-10 to CAUI-4, the upper GT quad is used for CAUI-4.
RECOMMENDED: For transceiver selections outside of these rules, contact AMD support or your local FAE.
See the UltraScale Architecture Clocking Resource User Guide (UG572) [Ref 6] for more information on Clock Region.