Transcode Bypass Mode Enabled - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The transmit portion of the RS-FEC engine operates in a single clock domain defined by tx_clk . The tx_reset signal is the asynchronous reset for the tx_clk domain.

The receive portion of the RS-FEC engine operates in a single clock domain defined by rx_clk . The rx_reset signal is the asynchronous reset for the rx_clk domain.