Transmit - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The LT transmit block constructs a 4,384-bit frame, which contains a frame delimiter, control channel, and link training sequence. It is formatted as shown in This Figure .

Figure D-3: Link Training Transmit

X-Ref Target - Figure D-3

X18836-link-training-transmit.jpg

RECOMMENDED: Xilinx recommends that the control channel bits not be changed by the link training algorithm while the transmit state machine is transmitting them, otherwise, they might be received incorrectly, possibly resulting in a DME error. This time begins when tx_SOF is asserted and ends at least 288 bit times later, or approximately 30 ns.

Note: Although the coefficient and status contain 128 bit times at the line rate, the actual signaling rate for these two fields is reduced by a factor of 8. Therefore, the DME clock rate is one quarter of the line rate.