Transmit 1588 Insertion and Timestamp Function - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The egress logic uses an operation/command bus to identify frames that require time stamping returned to the user, or frames for which a timestamp should be inserted. See Table: IEEE 1588 Interface – TX Path for a description of the command fields.

Transmit timestamping is illustrated in This Figure .

Figure 3-20: TX Timestamping

X-Ref Target - Figure 3-20

pg165_tx_timestamp_capture_x14344.jpg

As seen on the diagram, timestamping logic exists in two locations depending on whether 1-step or 2-step operation is desired. 1-step operation requires UDP checksum and FCS updates and therefore the FCS core logic is re-used.

The TS references are defined as follows:

TS1: The output timestamp signal when a 1-step operation is selected.

TS2: The output timestamp signal when a 2-step operation is selected.

TS2': The plane to which both timestamps are corrected.

TS2 always has a correction applied so that it is referenced to the TS2' plane. TS1 might or might not have the TS2' correction applied, depending on the value of the signal ctl_tx_ptp_latency_adjust[7:0] . The default value of this signal is 90 (decimal).

On the transmit side, a control input is provided by the client to the subsystem in parallel with the frame sent for transmission. This indicates, on a frame-by-frame basis, the 1588 function to perform (either no-operation, 1-step, or 2-step) and also indicates, for 1-step frames, whether there is a UDP checksum field to update.

If using the Ordinary Clock mode, then for both 1-step and 2-step operations, the full captured 80-bit ToD timestamp is returned to the client logic using the additional ports defined in Table: IEEE 1588 Interface – TX Path and Table: IEEE 1588 Interface – RX Path .

If using the Transparent clock mode, then for both 1-step and 2-step operations, the full captured 64-bit timestamp is returned to the client logic using the additional ports defined in Table: IEEE 1588 Interface – TX Path and Table: IEEE 1588 Interface – RX Path (with the upper bits of data set to zero as defined in the table).

If using the Ordinary Clock mode, then for a 1-step operation, the full captured 80-bit ToD timestamp is inserted into the frame. If using the Transparent clock mode, then for 1-step operation, the captured 64-bit timestamp is summed with the existing Correction Field contained within the frame and the summed result is overwritten into the original Correction Field of the frame. Supported frame types for 1-step timestamping are:

° Raw Ethernet

° UDP/IPv4

° UDP/IPv6

For 1-step UDP frame types, the UDP checksum is updated in accordance with IETF RFC 1624. For all 1-step frames, the Ethernet Frame Check Sequence (FCS) field is calculated after all frame modifications have been completed. For 2-step transmit operation, all Precision Time Protocol (PTP) frame types are supported.