Typical Operation - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The 100G Ethernet subsystem handles all protocol related functions to communicate to the other devices PCS and Ethernet MAC interface. This includes handshaking, synchronizing and error checking. You provide packet data through the Local Bus (LBUS) TX interface and receive packet data from the LBUS RX interface. The LBUS is designed to match commonly used packet bus protocols made common by the SPI4.2 and Interlaken protocols. A detailed description is given in User Side LBUS Interface .

The 100G Ethernet subsystem also has an option for AXI4-Stream user interface. You can transmit the packets through the AXI4-Stream TX interface and receive from the AXI4-Stream RX interface. A detailed description is given in User Side AXI4-Stream Interface .

The core is designed to be flexible and used in many different applications. The RX path does not perform any buffering other than the pipelining required to perform the required operations. Received data is passed directly to the user interface in a cut-through manner, allowing you the flexibility to implement any required buffering scheme. Also, the core TX path consists of a single pipeline with minimal buffering to provide reliable cut-through operation.

Additionally, the 100G Ethernet IP core can be configured to include the RS-FEC IP block in CAUI-4 mode to provide bit error detection and correction to protect the full 100 Gigabit data stream. Refer to UltraScale+ Device RS-FEC for Integrated 100G Ethernet for more information on this block.