UltraScale to UltraScale+ FPGA Enhancements - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2023-11-01
Version
3.1 English

The AMD UltraScale+™ Integrated 100G Ethernet IP is derived from AMD UltraScale™ Integrated 100G Ethernet IP (described in PG165 [Ref 7]) with a few enhancements and minor modifications, as documented in this appendix.