The read and write through the AXI4-Lite slave module interface is controlled by a state machine as shown in This Figure.
Functional description of each state is described as below:
•IDLE_STATE: By default, the FSM is in IDLE_STATE. When the user_read_req signal becomes High, it moves to READ_STATE. Otherwise, if the user_write_req signal is High, it moves to WRITE_STATE else it remains in IDLE_STATE.
•WRITE_STATE: The user state machine provides s_axi_awvalid, s_axi_awaddr, s_axi_wvalid, s_axi_wdata and s_axi_wstrb in this state to write to the register map through AXI. When s_axi_bvalid and s_axi_bready from AXI slave are High, it moves to ACK_STATE. If any write operation happens in any illegal addresses, the s_axi_bresp[1:0] indicates 2'b10 that asserts the write error signal.
•READ_STATE: The user state machine provides s_axi_arvalid and s_axi_araddr in this state to read from the register map through AXI. When s_axi_rvalid and s_axi_rready are High, it moves to ack_state. If any read operation happens from any illegal addresses, the s_axi_rresp[1:0] indicates 2'b10 that asserts the read error signal to the user logic.
•ACK_STATE: The state moves to IDLE_STATE.