Valid Cycles - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

Table: Valid TX Segmented LBUS Cycles shows possible valid TX segmented LBUS cycles.

Table 3-5: Valid TX Segmented LBUS Cycles

Clock Cycle

1

2

3

4

5

6

7

8

9

10

seg0

Dat

Idle

SOP

SOP

Dat

Dat

Idle

Dat

SOP

Idle

seg1

Dat

Idle

Dat

Dat

EOP

Dat

Idle

Dat

Dat

Idle

seg2

Dat

Idle

Dat

Dat

SOP

Dat

Idle

Dat

Dat

Idle

seg3

EOP

Idle

EOP

Dat

Dat

Dat

Idle

EOP

Dat

Idle

tx_rdyout

1

1

1

1

1

1

0

1

0

0

tx_ovfout

0

0

0

0

0

0

0

0

0

0

Cycle 1 shows the end of a packet transfer. If segment 3 (the EOP) is 16 bytes, then tx_mtyin3 is 0. If segment 3 is less than 16 bytes, then tx_mtyin3 is a value ranging from 0001b to 1111b.

Cycle 2 is idle and no data is transferred.

Cycle 3 shows the transfer of a packet having a length of 64 bytes.

CAUTION! Packets less than 64 bytes are considered undersized according to the Ethernet 802.3-2012 specification, and they are marked as undersized by the signal stat_tx_packet_small (for the transmit direction). Undersized packets might cause the core to lock up and must be avoided.

Cycle 4 shows the first part of the transfer of a packet greater than 64 bytes.

Cycle 5 shows the transfer of the end of the packet started in Cycle 4, as indicated by the EOP in Segment 1. Another packet might start during the same clock cycle, as indicated by the SOP in segment 2. There is no idle segment between the EOP and SOP.

Cycle 6 shows the transfer of additional data corresponding to the packet started during Cycle 5.

Cycle 7 is idle, even though the packet has not been completely transferred, due to the deassertion of tx_rdyout . This is the only instance where a packet transfer might be interrupted by idle cycles.

Cycle 8 shows the completion of the transfer of the packet started during Cycle 5.

During Cycle 9, tx_rdyout is deasserted. It is still possible to write data during that cycle because this is the first cycle it has been deasserted.

IMPORTANT: Xilinx recommends that no additional data be written in subsequent cycles until tx_rdyout is asserted again, or there can be an overflow condition indicated by tx_ovfout . This must be avoided.

Cycle 10 is idle due to the continued deassertion of tx_rdyout .