The clocking architecture for the 10/25G MAC with PCS/PMA clocking is illustrated below. This version of the subsystem includes FIFOs in the RX. There are three clock domains in the datapath, as illustrated by the dashed lines in the following figure.
Figure 1. 10G/25G MAC with PCS/PMA Clocking
- refclk_p0, refclk_n0, tx_serdes_refclk
refclkdifferential pair is required to be an input to the FPGA. The example design includes a buffer to convert this clock to a single-ended signal
refclk, which is used as the reference clock for the GT block. The
tx_serdes_refclkis directly derived from
refclk. Note that
refclkmust be chosen so that the
tx_serdes_refclkmeets the requirements of 802.3, which is within 100 ppm of 390.625 MHz for 25G, 156.25 MHz for 64-bit 10G, and 312.5 MHz for 32-bit 10G.
- This clock is used for clocking data into the TX AXI4-Stream Interface and it is also the reference clock for the
TX control and status signals. It is the same frequency as
rx_clk_outoutput signal is presented as a reference for the RX control and status signals processed by the RX core. It is the same frequency as the
rx_clkis available as
rx_core_clkis the input clk for RX core. This to you, which you must drive from the example design. You should drive the
rx_core_clkwith frequency that is equal to the
tx_clk. When FIFO is enabled, the most preferred mode of operation for system side datapath is to connect the
rx_core_clk. When connected in this manner, the RX AXI4-Stream Interface and the TX AXI4-Stream Interface are on the same clock domain. When FIFO is disabled,
rx_core_clkmust be driven by
dclksignal must be a convenient stable clock. It is used as a reference frequency for the GT helper blocks which initiate the GT itself. In the example design, a typical value is 75 MHz, which is readily derived from the 300 MHz clock available on the VCU107 evaluation board.Note: The actual frequency must be known to the GT helper blocks for proper operation.