AXI4-Stream Clocks and Resets - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2023-05-16
Version
4.1 English
Table 1. AXI4-Stream Interface Clock/Reset Signals
Name I/O Description Clock Domain
rx_clk_out O

rx_serdes_clk. Clocks RX interface between GT and the core. When in low latency buffer bypass mode this clock also clocks the AXI4-Stream RX interface.

See Clocking.
tx_clk_out O

Clocks TX AXI4-Stream Interface and full TX datapath.

See Clocking.
rx_reset I Reset for the RX circuits. This signal is active-High (1 = reset) and must be held High until clk is stable. The core handles synchronizing the rx_reset input to the appropriate clock domains within the core. Async
tx_reset I Reset for the TX circuits. This signal is active-High (1 = reset) and must be held High until clk is stable. The core handles synchronizing the tx_reset input to the appropriate clock domains within the core. Async
rx_core_clk I The rx_core_clk signal is used to clock the receive AXI4-Stream interface. When FIFO is not included, it must be driven by rx_clk_out. When FIFO is included, rx_core_clk can be driven by tx_clk_out, rx_clk_out, or another asynchronous clock at the same frequency. rx_core_clk