This section contains information about constraining the core in the Vivado Design Suite.
Required Constraints
The 10G/25G High Speed Ethernet Subsystem requires the specification of timing and other physical implementation constraints to meet the specified performance requirements. These constraints are provided in a Xilinx Device Constraints (XDC) file. Pinouts and hierarchy names in the generated XDC correspond to the provided example design of the 10G/25G High Speed Ethernet Subsystem.
To achieve consistent implementation results, an XDC containing these original, unmodified constraints must be used when a design is run through the AMD design tools. For additional details on the definition and use of an XDC specific constraints, see the Vivado Design Suite User Guide: Using Constraints (UG903).
Constraints provided in the 10G/25G High Speed Ethernet Subsystem have been verified through implementation and provide consistent results. Constraints can be modified, but modifications should only be made with a thorough understanding of the effect of each constraint.
Device, Package, and Speed Grade Selections
This section is not applicable for this IP subsystem.
Clock Frequencies
This section is not applicable for this subsystem.
Clock Management
This section is not applicable for this IP subsystem.
Clock Placement
This section is not applicable for this subsystem.
Banking
This section is not applicable for this IP subsystem.
Transceiver Placement
This section is not applicable for this IP subsystem.
I/O Standard and Placement
This section is not applicable for this IP subsystem.