Core Overview - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2023-05-16
Version
4.1 English

The following figure identifies the major functional blocks of the Timer Syncer IP. In this figure, only four instances of the port timer are shown for simplicity. The number of port instances are user selectable at the time of generating the core. This core supports up to 16 instances of port timers.

Figure 1. Timer Syncer IP Functional Block Diagram

The Timer Syncer IP contains all the functions and interfaces needed to implement a variety of ToD topologies and applications. Further, the IP can be controlled with either software or hardware devices.

The System Timer maintains time on the free-running system time clock (ts_clk) and provides a mechanism to synchronize the timer values with various other port timers, each of which might be clocked on their separate clocks (phy_clk).

The System Timer IP provides timer values in two formats: Timestamp format (or ToD format) and Correction Field (CF) format. The Timestamp format is comprised of 80 bits containing fields of unsigned positive seconds and nanoseconds, such as {seconds[47:0], nanoseconds[31:0] }. The Correction Field (CF) format is a signed 64b value in nanoseconds multiplied by 2+16.