IP Facts - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2023-11-10
Version
4.1 English
Facts Table
Subsystem Specifics
Supported Device Family 1

AMD Versal™ adaptive SoC

AMD UltraScale+™

AMD UltraScale™

Supported User Interfaces AXI4-Stream for variants with MAC

XGMII or 25GMII for PCS-only variants

Resources Performance and Resource Utilization web page
Provided with Subsystem
Design Files Encrypted register transfer level (RTL)
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Verilog
Supported S/W Driver Linux
Tested Design Flows 2
Design Entry Vivado Design Suite
Simulation For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
Synthesis Synopsys or Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 64710
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. For the supported versions of third-party tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
Note: To access the 25G specification, go to the 25G Ethernet Consortium website.