Per-Port Port Timer Interface - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2023-05-16
Version
4.1 English

m_denotes the port number (0≤ m ≤ 15).

Table 1. Per-Port Port Timer Interface
Signal Direction Clock Domain Description
tx_phy_clk_m I N/A Port TX PHY clock
rx_phy_clk_m I N/A Port RX PHY clock
tx_phy_rst_m I tx_phy_clk_m Port TX reset
rx_phy_rst_m I rx_phy_clk_m Port RX reset
tx_tod_sec_m[47:0] O tx_phy_clk_m Port TX timer seconds field
tx_tod_ns_m[31:0] O tx_phy_clk_m Port TX timer nano-seconds field
tx_tod_corr_m[63:0] O tx_phy_clk_m Port TX timer CF field
rx_tod_sec_m[47:0] O rx_phy_clk_m Port RX timer seconds field
rx_tod_ns_m[31:0] O rx_phy_clk_m Port RX timer nano-seconds field
rx_tod_corr_m[63:0] O rx_phy_clk_m Port RX timer CF field