Port Timer Registers - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2023-11-10
Version
4.1 English

Port timer register set is replicated for every port timer present (0 to 15) at the offsets listed for ports 1 to 15.

Table 1. Port Timer Registers
Offset Register Name Access Description
Port 0 Registers: 0x0200 to 0x023F
0x0200 TX0_CTIME_0 RW [31:0] - Snapshot of Port0 TX Timer’s CF Field [31:0]
0x0204 TX0_CTIME_1 RW

[30:0] - Snapshot of Port0 TX Timer’s CF Field [63:32]

[31] - Reserved

0x0208 TX0_PERIOD_0 RW

Port0 TX clock period expressed in 2-48 ns

For example, 3.2 ns is represented as

TX0_PERIOD_0[31:0] = 0x3333_3333

TX0_PERIOD_1[23:0] = 0x0003_3333

TX0_PERIOD_1[31:24] reserved

0x020C TX0_PERIOD_1 RW
0x0210 TX0_SYS_OFFSET RW [31:0] - Signed offset applied to Port0 TX Timer’s ToD output expressed in 2-16 ns.
0x0214 TX0_NS_SNAP RO

[29:0] - Snapshot of Port0 TX Timer’s Nano-second Field [29:0]

[31:30] - Reserved

0x0218 TX0_SEC_0_SNAP RO [31:0] - Snapshot of Port0 TX Timer’s Second Field [31:0]
0x021C TX0_SEC_1_SNAP RO

[15:0] - Snapshot of Port0 TX Timer’s Second Field [47:32]

[31:16] - Reserved

0x0220 RX0_CTIME_0 RW [31:0] - Snapshot of Port0 RX Timer’s CF Field [31:0]
0x0224 RX0_CTIME_1 RW

[30:0] - Snapshot of Port0 RX Timer’s CF Field [63:32]

[31] - Reserved

0x0228 RX0_PERIOD_0 RW

Port0 RX clock period expressed in 2-48 ns

For example, 3.2 ns is represented as

RX0_PERIOD_0[31:0] = 0x3333_3333

RX0_PERIOD_1[23:0] = 0x0003_3333

RX0_PERIOD_1[31:24] reserved

0x022C RX0_PERIOD_1 RW
0x0230 RX0_SYS_OFFSET RW [31:0] - Signed offset applied to Port0 RX Timer’s ToD output expressed in 2-16 ns.
0x0234 RX0_NS_SNAP RO

[29:0] - Snapshot of Port0 RX Timer’s Nano-second Field [29:0]

[31:30] - Reserved

0x0238 RX0_SEC_0_SNAP RO [31:0] - Snapshot of Port0 RX Timer’s Second Field [31:0]
0x023C RX0_SEC_1_SNAP RO

[15:0] - Snapshot of Port0 RX Timer’s Second Field [47:32]

[31:16] - Reserved

0x0240 CORE_TX0_PERIOD_ 0 RO Port0 TX clock period configured in core, expressed in 2-48 ns.

For example, 3.2 ns is represented as:

CORE_TX0_PERIOD_ 0 = 0x3333_3333

CORE_TX0_PERIOD_ 1 = 0x0003_3333

CORE_TX0_PERIOD_ 1[31:24] reserved

0x0244 CORE_TX0_PERIOD_ 1 RO
0x0248 CORE_RX0_PERIOD_ 0 RO Port0 RX clock period configured in core, expressed in 2-48 ns.

For example, 3.2 ns is represented as:

CORE_RX0_PERIOD_ 0 = 0x3333_3333

CORE_RX0_PERIOD_ 1 = 0x0003_3333

CORE_RX0_PERIOD_ 1[31:24] reserved

0x024C CORE_RX0_PERIOD_ 1 RO
0x0250 PORT0_SEC_ OFFSET_0   PORT0_SEC_SYS_OFFSET_1[15:0], PORT0_SEC_SYS_OFFSET_0[31:0]} - Represents Port timer 48b seconds field signed offset value.

PORT0_NS_SYS_OFFSET_0[29:0] - Represents Port timer 30b nano second field signed offset value.

Signed bit interpreted as follows for PORT0_SEC_SYS_OFFSET:

If [47] = 1’b1 then subtract from port timer

If [47] = 1’b0 then add to port timer

These registers are used to apply large port specific offset.

A write to PORT0_NS_SYS_OFFSET_0 is required to trigger the application of the Port’s offset.

0x0254 PORT0_SEC_ OFFSET_1  
0x0258 PORT0_NS_OFFSET_0  
0x025C – 0x027F Reserved N/A Reserved
Port 1 Registers: 0x0280 to 0x02FF
Port 2 Registers: 0x0300 to 0x037F
Port 3 Registers: 0x0380 to 0x03FF
Port 4 Registers: 0x0400 to 0x047F
Port 5 Registers: 0x0480 to 0x04FF
Port 6 Registers: 0x0500 to 0x057F
Port 7 Registers: 0x0580 to 0x05FF
Port 8 Registers: 0x0600 to 0x067F
Port 9 Registers: 0x0680 to 0x06FF
Port 10 Registers: 0x0700 to 0x077F
Port 11 Registers: 0x0780 to 0x07FF
Port 12 Registers: 0x0800 to 0x087F
Port 13 Registers: 0x0880 to 0x08FF
Port 14 Registers: 0x0900 to 0x097F
Port 15 Registers: 0x0980 to 0x09FF