Port/Signal Comparison - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2023-11-10
Version
4.1 English

There are significant differences in the names and functions of the signals and parameters. Because it is difficult to draw a one-to-one comparison, the following tables are based on features and their presentation in the two IP cores.

Transmitter Configuration

The legacy XGEMAC used the mac_tx_configuration_vector[368:0] for all TX configuration whereas the 10G/25G High Speed Ethernet IP deploys various signals for the same purpose. The following table draws a comparison.

Table 1. Transmitter Configuration Comparison
Feature Legacy XGEMAC 10/25G High Speed Ethernet IP
Legacy Pause Refresh Value mac_tx_configuration_vector[367:352]  
TX Priority 7 Pause Quanta refresh value mac_tx_configuration_vector[351:336] ctl_tx_pause_refresh_timer7[15:0]
TX Priority 7 Pause Quanta mac_tx_configuration_vector[335:320] ctl_tx_pause_quanta7[15:0]
TX Priority 6 Pause Quanta refresh value mac_tx_configuration_vector[319:304] ctl_tx_pause_refresh_timer6[15:0]
TX Priority 6 Pause Quanta mac_tx_configuration_vector[303:288] ctl_tx_pause_quanta6[15:0]
TX Priority 5 Pause Quanta refresh value mac_tx_configuration_vector[287:272] ctl_tx_pause_refresh_timer5[15:0]
TX Priority 5 Pause Quanta mac_tx_configuration_vector[271:256] ctl_tx_pause_quanta5[15:0]
TX Priority 4 Pause Quanta refresh value mac_tx_configuration_vector[255:240] ctl_tx_pause_refresh_timer4[15:0]
TX Priority 4 Pause Quanta mac_tx_configuration_vector[239:224] ctl_tx_pause_quanta4[15:0]
TX Priority 3 Pause Quanta refresh value mac_tx_configuration_vector[223:208] ctl_tx_pause_refresh_timer3[15:0]
TX Priority 3 Pause Quanta mac_tx_configuration_vector[207:192] ctl_tx_pause_quanta3[15:0]
TX Priority 2 Pause Quanta refresh value mac_tx_configuration_vector[191:176] ctl_tx_pause_refresh_timer2[15:0]
TX Priority 2 Pause Quanta mac_tx_configuration_vector[175:160] ctl_tx_pause_quanta2[15:0]
TX Priority 1 Pause Quanta refresh value mac_tx_configuration_vector[159:144] ctl_tx_pause_refresh_timer1[15:0]
TX Priority 1 Pause Quanta mac_tx_configuration_vector[143:128] ctl_tx_pause_quanta1[15:0]
TX Priority 0 Pause Quanta refresh value mac_tx_configuration_vector[127:112] ctl_tx_pause_refresh_timer0[15:0]
TX Priority 0 Pause Quanta mac_tx_configuration_vector[111:96] ctl_tx_pause_quanta0[15:0]
TX Priority 7 Flow Control Enable mac_tx_configuration_vector[95] ctl_tx_pause_enable[7]
TX Priority 6 Flow Control Enable mac_tx_configuration_vector[94] ctl_tx_pause_enable[6]
TX Priority 5 Flow Control Enable mac_tx_configuration_vector[93] ctl_tx_pause_enable[5]
TX Priority 4 Flow Control Enable mac_tx_configuration_vector[92] ctl_tx_pause_enable[4]
TX Priority 3 Flow Control Enable mac_tx_configuration_vector[91] ctl_tx_pause_enable[3]
TX Priority 2 Flow Control Enable mac_tx_configuration_vector[90] ctl_tx_pause_enable[2]
TX Priority 1 Flow Control Enable mac_tx_configuration_vector[89] ctl_tx_pause_enable[1]
TX Priority 0 Flow Control Enable mac_tx_configuration_vector[88] ctl_tx_pause_enable[0]
Auto XON enable mac_tx_configuration_vector[81]  
Priority flow control enable mac_tx_configuration_vector[80]  
TX Pause Frame Source Address mac_tx_configuration_vector[79:32] ctl_tx_pause_da[47:0]
TX MTU Size mac_tx_configuration_vector[30:16] Not required because the TX can handle any size frame presented to the IP.
TX MTU enable mac_tx_configuration_vector[14] Not applicable because there is no need to set the TX. MTU does not have to be set.
Deficit Idle Count Enable mac_tx_configuration_vector[10] Not supported
TX LAN/WAN mode mac_tx_configuration_vector[9]

This feature is not available as-is. The 10G/25G High Speed Ethernet IP always maintains the average IPG per the IEEE 802.3 spec.

However you can design the user logic to insert idles using ctl_send_idle and increase the IPG value using ctl_tx_ipg_value[3:0] to meet the OC-192 SONET requirements.

TX IFG Adjust enable mac_tx_configuration_vector[8] ctl_tx_ipg_value sets the appropriate value of the custom IPG/IFG
TX Preserve Preamble Enable mac_tx_configuration_vector[7] ctl_tx_custom_preamble_enable enables the use of a custom preamble. Tx_preamblein presents the custom preamble and rx_preambleout has the preamble field from the received frame.
TX Flow control Enable mac_tx_configuration_vector[5] ctl_tx_pause_enable[8:0]
TX Jumbo Frame Enable mac_tx_configuration_vector[4] Not required
TX In-band FCS enable mac_tx_configuration_vector[3] ctl_tx_fcs_ins_enable
TX VLAN enable mac_tx_configuration_vector[2] Not required
TX Enable mac_tx_configuration_vector[1] ctl_tx_enable
TX Reset mac_tx_configuration_vector[0] tx_reset

Receiver Configuration

The legacy XGEMAC used the rx_configuration_vector[95:0] for all RX configuration whereas the 10G/25G High Speed Ethernet IP core deploys various signals for the same purpose. The following table draws a comparison.

Table 2. Receiver Configuration Comparison
Feature Legacy XGEMAC 10/25G High Speed Ethernet IP
RX Priority 7-0 Flow control enable rx_configuration_vector[95:88] ctl_rx_pause_enable[8:0]
Priority Flow Control Enable rx_configuration_vector[80]  
RX Pause Frame SA rx_configuration_vector[79:32] ctl_rx_pause_sa[47:0]
RX MTU size rx_configuration_vector[30:16] Set using ctl_rx_max_packet_len and ctl_rx_min_packet_len signals.
RX MTU Enable rx_configuration_vector[14] Not required.
Reconciliation Sublayer Fault Inhibit rx_configuration_vector[10] Design user logic to set ctl_tx_send_idle when RFI is received.
Control Frame Length check Disable rx_configuration_vector[9] Not available
RX Length/Type Error disable rx_configuration_vector[8] The length/type error cannot be disabled on the 10/25G High Speed Ethernet IP core.
RX preserve preamble enable rx_configuration_vector[7] ctl_rx_custom_preamble_enable
RX Flow control enable rx_configuration_vector[5] ctl_rx_pause_enable[8:0]
RX Jumbo Frame Enable rx_configuration_vector[4] Set using the ctl_rx_max_packet_len signal.
RX in-band FCS enable rx_configuration_vector[3] ctl_rx_delete_fcs
RX VLAN enable rx_configuration_vector[2] Up to the user logic to implement this functionality.
RX enable rx_configuration_vector[1] ctl_rx_enable
RX reset rx_configuration_vector[0] rx_reset

Status Vector

Table 3. Status Vector Comparison
Feature Legacy XGEMAC 10/25G High Speed Ethernet IP
Remote Fault RX status_vector[1] This feature is not available.
Local Fault RX status_vector[0] This feature is not available.

TX Statistics

The legacy XGEMAC used the tx_statistics_vector[25:0] for all TX statistics whereas the 10G/25G High Speed Ethernet IP core deploys various signals for the same purpose. The following table draws a comparison.

Table 4. TX Statistics Comparison
Feature Legacy XGEMAC 10/25G High Speed Ethernet MAC
PFC Frame Transmitted tx_statistics_vector[26] stat_tx_user_pause
Pause Frame Transmitted tx_statistics_vector[25] stat_tx_pause
Bytes Valid tx_statistics_vector[24:21] stat_tx_total_good_bytes
VLAN Frame tx_statistics_vector[20] stat_tx_vlan
Frame length count tx_statistics_vector[19:5] stat_tx_packet_* signals that can also be used for the packet histogram.
Control Frame tx_statistics_vector[4]  
Underrun Frame tx_statistics_vector[3]  
Multicast Frame tx_statistics_vector[2] stat_tx_multicast
Broadcast Frame tx_statistics_vector[1] stat_tx_broadcast
Successful Frame tx_statistics_vector[0] stat_tx_total_good_packets
TX statistics Valid tx_statistics_valid Not required

RX Statistics

The legacy XGEMAC used the rx_statistics_vector[30:0] for all RX statistics whereas the 10G/25G High Speed Ethernet IP core deploys various signals for the same purpose. The following table draws a comparison.

Table 5. RX Statistics Comparison
Feature Legacy XGEMAC 10/25G High Speed Ethernet MAC
PFC Frame rx_statistics_vector[30] stat_rx_user_pause
Length/Type out of range rx_statistics_vector[29] stat_rx_inrangeerr
Bad Opcode rx_statistics_vector[28]  
Flow Control Frame rx_statistics_vector[27] stat_rx_pause
Bytes Valid rx_statistics_vector[26:23] stat_rx_total_bytes[3:0]
VLAN Frame rx_statistics_vector[22] stat_rx_vlan
Out of Bounds rx_statistics_vector[21] stat_rx_toolong
Control Frame rx_statistics_vector[20]  
Frame Length Count rx_statistics_vector [19:5] stat_rx_total_good_bytes [13:0]
Multicast Frame rx_statistics_vector [4] stat_rx_multicast
Broadcast frame rx_statistics_vector [3] stat_rx_broadcast
FCS Error rx_statistics_vector [2] stat_rx_packet_bad_fcs
Bad frame rx_statistics_vector [1] stat_rx_total_good_packets sampled as 0
Good Frame rx_statistics_vector [0] stat_rx_total_good_packets sampled as 1
RX statistics Valid rx_statistics_valid Not required

Register Space

Both the legacy XGEMAC and the 10/25G High Speed Ethernet IP core provide an AXI User Interface. While much of the configuration parameters are similar, the registers and the memory map of the registers are different between the two IP cores. The following sections discuss the comparison between the configuration, statistics and other registers.

TX Configuration Registers

Table 6. TX Configuration Registers Comparison
Feature Legacy XGEMAC 10/25G HSEC
TX MTU Size @0x418: Transmitter MTU Configuration Word [14:0] Not required because the TX can handle any size frame presented to the IP.
TX MTU enable @0x418: Transmitter MTU Configuration Word [16] Not applicable because there is no need to set the TX MTU.
Deficit Idle Count Enable @0x408: Transmitter Configuration Word[24] Not supported
TX LAN/WAN mode @0x408: Transmitter Configuration Word[26]

This feature is not available as-is. The 10G/25G High Speed Ethernet IP Subsystem always maintains the average IPG per the IEEE 802.3 spec.

However, you can design the user logic to insert idles using @0x000C: CONFIGURATION_TX_REG1[5] ctl_send_idle and increase the IPG value using @0x000C: CONFIGURATION_TX_REG1[13:10] ctl_tx_ipg_value[3:0] to meet the OC-192 SONET requirements.

TX IFG Adjust enable @0x408: Transmitter Configuration Word[25] @0x000C: CONFIGURATION_TX_REG1[13:10] ctl_tx_ipg_value sets the appropriate value of the custom IPG/IFG.
TX Preserve Preamble Enable @0x408: Transmitter Configuration Word[23] @0x000C: CONFIGURATION_TX_REG1[18] ctl_tx_custom_preamble_enable enables the use of custom preamble. Tx_preamblein presents the custom preamble and rx_preambleout has the preamble field from the received frame.
TX Flow control Enable @0x40C: Flow control Configuration register [30] ctl_tx_pause_enable[8:0]
TX Jumbo Frame Enable @0x408: Transmitter Configuration Word[30] Not required.
TX In-band FCS enable @0x408: Transmitter Configuration Word[29] @0x000C: CONFIGURATION_TX_REG1[1] ctl_tx_fcs_ins_enable
TX VLAN enable @0x408: Transmitter Configuration Word[27] Not required.
TX Enable @0x408: Transmitter Configuration Word [28] @0x000C: CONFIGURATION_TX_REG1[0] ctl_tx_enable
TX Reset @0x408: Transmitter Configuration Word [31] @0x0004: RESET_REG[31] tx_reset

RX Configuration

Table 7. RX Configuration Comparison
Feature Legacy XGEMAC 10/25G High Speed Ethernet IP Core
RX Priority 7-0 Flow control enable Bit 95:88 @0x0094: CONFIGURATION_RX_FLOW_CONTROL_REG1 [7:0]
Priority Flow Control Enable Bit 80 Does not support legacy PFC
RX Pause Frame SA @0x404: Receiver Configuration Word 1[47:32], @0x400: Receiver Configuration Word 0

@0x00C4: CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_MSB[15:0],

@0x00C0: CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_LSB

RX MTU size @0x414: Receiver MTU Configuration Word [14:0] Set using @0x0018: CONFIGURATION_RX_MTU[30:16] ctl_rx_max_packet_len and @0x0018: CONFIGURATION_RX_MTU[7:0] ctl_rx_min_packet_len signals
RX MTU Enable @0x414: Receiver MTU Configuration Word [16] Not required.
Reconciliation Sublayer Fault Inhibit @0x410: Reconciliation Sublayer Configuration Word [27] Design user logic to set @0x000C: CONFIGURATION_TX_REG1[5] ctl_tx_send_idle when RFI is received
Control Frame Length check Disable @0x404: Receiver Configuration Word 1[24] Not available
RX Length/Type Error disable @0x404: Receiver Configuration Word 1[25] The length/type error cannot be disabled on the 10/25G High Speed Ethernet Subsystem.
RX preserve preamble enable @0x404: Receiver Configuration Word 1[26] @0x0014: CONFIGURATION_RX_REG1[11] ctl_rx_custom_preamble_enable
RX Flow control enable @0x40C: Flow Control Configuration Register [29] @0x0094: CONFIGURATION_RX_FLOW_CONTROL[8:0] ctl_rx_pause_enable[8:0]
RX Jumbo Frame Enable @0x404: Receiver Configuration Word 1[30] Set using ctl_rx_max_packet_len signal
RX in-band FCS enable @0x404: Receiver Configuration Word 1[29] @0x0014: CONFIGURATION_RX_REG1[1] ctl_rx_delete_fcs
RX VLAN enable @0x404: Receiver Configuration Word 1[27] Up to the user logic to implement this functionality
RX enable @0x404: Receiver Configuration Word 1[28] @0x0014: CONFIGURATION_RX_REG1[0] ctl_rx_enable
RX reset @0x404: Receiver Configuration Word 1[31] @0x0004: RESET_REG[30] rx_reset

Status Vector

Table 8. Status Vector Comparison
Feature Legacy XGEMAC 10/25G High Speed Ethernet IP
Remote Fault RX @0x410: Reconciliation Sublayer Configuration Word[29] This feature is not available.
Local Fault RX @0x410: Reconciliation Sublayer Configuration Word[28] This feature is not available.

Statistics Counters

The following table lists the different statistics counters and their addresses.

Table 9. Statistics Counters
Address (Hex) Register Register Address (Hex)
0x200 Received Bytes (LSW) STAT_RX_TOTAL_BYTES_LSB 0x0808
0x204 Received Bytes (MSW) STAT_RX_TOTAL_BYTES_MSB 0x080C
0x208 Transmitted Bytes (LSW) STAT_TX_TOTAL_BYTES_LSB 0x0710
0x20C Transmitted Bytes (MSW) STAT_TX_TOTAL_BYTES_MSB 0x0714
0x210 Undersize Frames Received (LSW) STAT_RX_UNDERSIZE _LSB 0x0898
0x214 Undersize Frames Received (MSW) STAT_RX_UNDERSIZE_MSB 0x089C
0x218 Fragment Frames Received (LSW) STAT_RX_FRAGMENT_LSB 0x08A0
0x21C Fragment Frames Received (MSW) STAT_RX_FRAGMENT_MSB 0x08A4
0x220 64-byte frames received OK (LSW) STAT_RX_PACKET_64_BYTES_LSB 0x0828
0x224 64-byte frames received OK (MSW) STAT_RX_PACKET_64_BYTES_MSB 0x082C
0x228 65-127 byte frames received OK (LSW) STAT_RX_PACKET_65_127_BYTES_LSB 0x0830
0x22C 65-127 byte frames received OK (MSW) STAT_RX_PACKET_65_127_BYTES_MSB 0x0834
0x230 128-255 byte frames received OK (LSW) STAT_RX_PACKET_128_255_BYTES_LSB 0x0838
0x234 128-255 byte frames received OK (MSW) STAT_RX_PACKET_128_255_BYTES_MSB 0x083C
0x238 256-511 byte frames received OK (LSW) STAT_RX_PACKET_256_511_BYTES_LSB 0x0840
0x23C 256-511 byte frames received OK (MSW) STAT_RX_PACKET_256_511_BYTES_MSB 0x0844
0x240 512-1023 byte frames received OK (LSW) STAT_RX_PACKET_512_1023_BYTES_LSB 0x0848
0x244 512-1023 byte frames received OK (MSW) STAT_RX_PACKET_512_1023_BYTES_MSB 0x084C
0x248 1024 – MaxFrameSize byte frames received OK (LSW) STAT_RX_PACKET_1024_1518_BYTES_LSB 0x0850
STAT_RX_PACKET_1519_1522_BYTES_LSB 0x0858
STAT_RX_PACKET_1523_1548_BYTES_LSB 0x0860
STAT_RX_PACKET_1549_2047_BYTES_LSB 0x0868
STAT_RX_PACKET_2048_4095_BYTES_LSB 0x0870
STAT_RX_PACKET_4096_8191_BYTES_LSB 0x0878
STAT_RX_PACKET_8192_9215_BYTES_LSB 0x0880
STAT_RX_PACKET_LARGE_LSB 0x0888
0x24C 1024 – MaxFrameSize byte frames received OK (MSW) STAT_RX_PACKET_1024_1518_BYTES_MSB 0x0854
STAT_RX_PACKET_1519_1522_BYTES_MSB 0x085C
STAT_RX_PACKET_1523_1548_BYTES_MSB 0x0864
STAT_RX_PACKET_1549_2047_BYTES_MSB 0x086C
STAT_RX_PACKET_2048_4095_BYTES_MSB 0x0874
STAT_RX_PACKET_4096_8191_BYTES_MSB 0x087C
STAT_RX_PACKET_8192_9215_BYTES_MSB 0x0884
STAT_RX_PACKET_LARGE_MSB 0x088C
0x250 Oversize frames received OK (LSW) STAT_RX_OVERSIZE_LSB 0x08A8
0x254 Oversize frames received OK (MSW) STAT_RX_OVERSIZE_MSB 0x08AC
0x258 64-byte frames transmitted OK (LSW) STAT_TX_PACKET_64_BYTES_LSB 0x0720
0x25C 64-byte frames transmitted OK (MSW) STAT_TX_PACKET_64_BYTES_MSB 0x0724
0x260 65-127 byte frames transmitted OK (LSW) STAT_TX_PACKET_65_127_BYTES_LSB 0x0728
0x264 65-127 byte frames transmitted OK (MSW) STAT_TX_PACKET_65_127_BYTES_MSB 0x072C
0x268 128-255 byte frames transmitted OK (LSW) STAT_TX_PACKET_128_255_BYTES_LSB 0x0730
0x26C 128-255 byte frames transmitted OK (MSW) STAT_TX_PACKET_128_255_BYTES_MSB 0x0734
0x270 256-511 byte frames transmitted OK (LSW) STAT_TX_PACKET_256_511_BYTES_LSB 0x0738
0x274 256-511 byte frames transmitted OK (MSW) STAT_TX_PACKET_256_511_BYTES_MSB 0x073C
0x278 512-1023 byte frames transmitted OK (LSW) STAT_TX_PACKET_512_1023_BYTES_LSB 0x0740
0x27C 512-1023 byte frames transmitted OK (MSW) STAT_TX_PACKET_512_1023_BYTES_MSB 0x0744
0x280 1024 – MaxFrameSize byte frames transmitted OK (LSW) STAT_TX_PACKET_1024_1518_BYTES_LSB 0x0748
STAT_TX_PACKET_1519_1522_BYTES_LSB 0x0750
STAT_TX_PACKET_1523_1548_BYTES_LSB 0x0758
STAT_TX_PACKET_1549_2047_BYTES_LSB 0x0760
STAT_TX_PACKET_2048_4095_BYTES_LSB 0x0768
STAT_TX_PACKET_4096_8191_BYTES_LSB 0x0770
STAT_TX_PACKET_8192_9215_BYTES_LSB 0x0778
STAT_TX_PACKET_LARGE_LSB 0x0780
0x284 1024 – MaxFrameSize byte frames transmitted OK (MSW) STAT_TX_PACKET_1024_1518_BYTES_MSB 0x074C
STAT_TX_PACKET_1519_1522_BYTES_MSB 0x0754
STAT_TX_PACKET_1523_1548_BYTES_MSB 0x075C
STAT_TX_PACKET_1549_2047_BYTES_MSB 0x0764
STAT_TX_PACKET_2048_4095_BYTES_MSB 0x076C
STAT_TX_PACKET_4096_8191_BYTES_MSB 0x0774
STAT_TX_PACKET_8192_9215_BYTES_MSB 0x077C
STAT_TX_PACKET_LARGE_MSB 0x0784
0x288 Oversize frames transmitted OK (LSW) N/A  
0x28C Oversize frames transmitted OK (MSW)    
0x290 Frames received OK (LSW) STAT_RX_TOTAL_GOOD_PACKETS_LSB 0x0810
0x294 Frames received OK (MSW) STAT_RX_TOTAL_GOOD_PACKETS_MSB 0x0814
0x298 Frame Check Sequence Error (LSW) STAT_RX_PACKET_BAD_FCS_LSB 0x08C8
0x29C Frame Check Sequence Error (MSW) STAT_RX_PACKET_BAD_FCS_MSB 0x08CC
0x2A0 Broadcast Frames received OK (LSW) STAT_RX_BROADCAST_LSB 0x8E8
0x2A4 Broadcast Frames received OK (MSW) STAT_RX_BROADCAST_MSB 0x8EC
0x2A8 Multicast Frames received OK (LSW) STAT_RX_MULTICAST_LSB 0x08E0
0x2AC Multicast Frames received OK (MSW) STAT_RX_MULTICAST_MSB 0x08E4
0x2B0 Control Frames received OK (LSW)    
0x2B4 Control Frames received OK (MSW)    
0x2B8 Length/Type out of range (LSW) STAT_RX_INRANGEERR_LSB 0x0908
0x2BC Length/Type out of range (MSW) STAT_RX_INRANGEERR_MSB 0x090C
0x2C0 VLAN tagged frames received OK (LSW) STAT_RX_VLAN_LSB 0x08F0
0x2C4 VLAN tagged frames received OK (MSW) STAT_RX_VLAN_MSB 0x08F4
0x2C8 PAUSE frames received OK (LSW) STAT_RX_PAUSE_LSB 0x08F8
0x2CC PAUSE frames received OK (MSW) STAT_RX_PAUSE_MSB 0x08FC
0x2D0 Control frames received with unsupported opcode (LSW)    
0x2D4 Control frames received with unsupported opcode (MSW)    
0x2D8 Frames transmitted OK (LSW) STAT_TX_TOTAL_GOOD_PACKETS_LSB 0x0708
0x2DC Frames transmitted OK (MSW) STAT_TX_TOTAL_GOOD_PACKETS_MSB 0x070C
0x2E0 Broadcast Frames transmitted OK (LSW) STAT_TX_BROADCAST_LSB 0x07E0
0x2E4 Broadcast Frames transmitted OK (MSW) STAT_TX_BROADCAST_MSB 0x07E4
0x2E8 Multicast Frames transmitted OK (LSW) STAT_TX_MULTICAST_LSB 0x07D8
0x2EC Multicast Frames transmitted OK (MSW) STAT_TX_MULTICAST_MSB 0x07DC
0x2F0 Underrun errors (LSW)    
0x2F4 Underrun errors (MSW)    
0x2F8 Control Frames transmitted OK (LSW)    
0x2FC Control Frames transmitted OK (MSW)    
0x300 VLAN tagged frames transmitted OK (LSW) STAT_TX_VLAN_LSB 0x07E8
0x304 VLAN tagged frames transmitted OK (MSW) STAT_TX_VLAN_MSB 0x07EC
0x308 PAUSE frames transmitted OK (LSW) STAT_TX_PAUSE_LSB 0x07F0
0x30C PAUSE frames transmitted OK (MSW) STAT_TX_PAUSE_MSB 0x07F4

Pause Processing

The following section outlines the configuration for priority based flow control.

Table 10. Pause Processing
Address (Hex) Register Register Address (Hex)
0x480 Priority 0 Quanta Register CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1 [15:0] 0x0058
0x484 Priority 1 Quanta Register CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1 [31:16] 0x0058
0x488 Priority 2 Quanta Register CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2 [15:0] 0x005C
0x48C Priority 3 Quanta Register CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2 [31:16] 0x005C
0x490 Priority 4 Quanta Register CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3 [15:0] 0x0060
0x494 Priority 5 Quanta Register CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3 [31:16] 0x0060
0x498 Priority 6 Quanta Register CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4 [15:0] 0x0064
0x49C Priority 7 Quanta Register CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4 [31:16] 0x0064
0x4A0 Legacy Pause Refresh Register Does not support Legacy PFC  

MDIO Control Registers

The 10G/25G High Speed Ethernet IP does not provide an MDIO station master and thus does not have any of the MDIO control registers.

Interrupt Registers

Typically interrupts are generated after an MDIO operation to indicate completion; because there is no MDIO master there are no interrupt registers.

PCS/PMA MDIO register map

Again, because there is no MDIO interface provided, there are no MDIO registers for the PCS/PMA interface.

AXI4-Stream Interface

The 10G/25G High Speed Ethernet IP Subsystem provides both 64-bit and 32-bit AXI4-Stream interfaces for the datapath as does the Legacy 10G Ethernet IP Subsystem. Note the following difference in the use of tuser bits on the RX interface. The table below compares the definitions of the tuser signals on both TX and RX.

Table 11. Comparison of the Definitions of the tuser Signals in Both TX and RX
Signal Legacy XGEMAC 10/25G High Speed Ethernet IP
RX AXI4-Stream tuser

m_axis_rx_tuser

AXI4-Stream User Sideband interface.

  • 0 indicates a bad packet has been received.
  • 1 indicates a good packet has been received

rx_axis_tuser

AXI4-Stream User Sideband interface.

  • 1 indicates a bad packet has been received.
  • 0 indicates a good packet has been received.
TX AXI4-Stream tuser

s_axis_tx_tuser

AXI4-Stream user signal used to indicate explicit underrun

tx_axis_tuser

AXI4-Stream User Sideband interface.

  • 1 indicates a bad packet has been received.
  • 0 indicates a good packet has been received.