STAT_GT_WIZ_REG: 04A0 - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2023-11-10
Version
4.1 English
Table 1. STAT_GT_WIZ_REG: 04A0
Bits Default Type Signal
0 0 RO gtwiz_reset_tx_done
1 0 RO gtwiz_reset_rx_done
  1. This register indicates that the GT is out of reset and the recovered TX/RX clocks are stable.
  2. The user needs to first read 0x04A0 register (STAT_GT_WIZ_REG) and wait till the value is 2'b11. Then, perform the next operations such as reading the Block Lock register (0x040C).