SWITCH_CORE_SPEED_REG: 0138 - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2023-11-10
Version
4.1 English
Table 1. SWITCH_CORE_SPEED_REG: 0138
Bits Default Type Signal
0 0 RW axi_ctl_core_mode_switch

For Runtime Switch mode only. A write 1 enables the mode switch between 10G and 25G. This is a clear on the write register. This is an input to the trans debug module that performs the GT DRP operations.