This document details the features of the 10G/25G Ethernet Subsystem as defined by the 25G Ethernet Consortium. PCS functionality is defined by IEEE Standard 802.3, 2015, Clause 49, Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R. For 25G operation, clock frequencies are increased to provide a serial interface operating at 25.78125 Gbps to leverage the latest high-speed serial transceivers. The low latency design is optimized for AMD UltraScale™ architecture devices.