Transceiver Core and Status Debug Ports - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2023-11-10
Version
4.1 English

The ports in the following table are available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab or Enable Additional GT Control/Status and DRP Ports is selected from the GT Selection and Configuration tab.

For port descriptions, see UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182), UltraScale Architecture GTH Transceivers User Guide( UG576) and UltraScale Architecture GTY Transceivers User Guide( UG578).

Table 1. Transceiver Core and Status Debug Ports
Name Size I/O
gt_dmonitorout_* 16 O
gt_eyescandataerror_* 1 O
gt_eyescanreset_* 1 I
gt_eyescantrigger_* 1 I
gt_pcsrsvdin_* 16 I
gt_rxbufreset_* 1 I
gt_rxbufstatus_* 3 O
gt_rxcdrhold_* 1 I
gt_rxcommadeten_* 1 I
gt_rxdfeagchold_* 1 I
gt_rxdfelpmreset_* 1 I
gt_rxlatclk_* 1 I
gt_rxlpmen_* 1 I
gt_rxpcsreset_* 1 I
gt_rxpmareset_* 1 I
gt_rxpolarity_* 1 I
gt_rxprbscntreset_* 1 I
gt_rxprbslocked_* 1 O
gt_rxprbserr_* 1 I
gt_rxprbssel_* 4 I
gt_rxrate_* 3 I
gt_rxslide_in_* 1 I
gt_rxstartofseq_* 2 O
gt_txresetdone_* 1 O
gt_txbufstatus_* 2 O
gt_txdiffctrl_* 5 I
gt_txinhibit_* 1 I
gt_txlatclk_* 1 I
gt_txmaincursor_* 7 I
gt_txpcsreset_* 1 I
gt_txpmareset_* 1 I
gt_txpolarity_* 1 I
gt_txprbsforceerr_* 1 I
gt_txprbssel_* 4 I
gt_txprecursor_* 5 I
gtwiz_reset_tx_datapath_* 1 I
gtwiz_reset_rx_datapath_* 1 I
gt_drpclk_* 1 1 I
gt_drpdo_* 1 16 O
gt_drprdy_* 1 1 O
gt_drpen_* 1 1 I
gt_drpwe_* 1 1 I
gt_drpaddr_* 1 10 I
gt_drpdi_* 1 16 I
gt_drprst_* 1 I
  1. This port is available for non-Versal device only.