Ports under this section are available when Ethernet MAC+PCS/PMA with the 128-bit Straddle Packet AXI4-Stream option is selected from the Configuration tab.
Name | Size | I/O | Description |
---|---|---|---|
tx_unfout_* | 1 | O |
Underflow signal for TX path from core. If tx_unfout_* is sampled as 1, a violation has occurred meaning the current packet is corrupted. Error control blocks are transmitted as long as the underflow condition persists. It is up to the user logic to ensure a complete packet is input to the core without under-running the TX data path interface. Note: When this signal sampled as 1, you
must apply tx_reset/sys_reset to recover the core from the
underflow issue. tx_reset resets the TX path only and sys_reset
recovers the complete system.
|
tx_axis_tready_* | 1 | O | TX path ready signal from core. |
tx_axis_tvalid_* | 1 | I | Transmit AXI4-Stream Data valid. |
tx_axis_tdata_* | 128 | I | Transmit AXI4-Stream Data bus. |
tx_axis_tuser_* | 70 | I | TX segment and packet information signal. tx_axis_tuser_0[69:0] |
69 - tx_axis_tuser_err1 | |||
68:66 - tx_axis_tuser_mty1[2:0] | |||
65 - tx_axis_tuser_eop1 | |||
64 - tx_axis_tuser_sop1 | |||
63 - tx_axis_tuser_ena1 | |||
62 - tx_axis_tuser_err0 | |||
61:59 - tx_axis_tuser_mty0[2:0] | |||
58 - tx_axis_tuser_eop0 | |||
57 - tx_axis_tuser_sop0 | |||
56- tx_axis_tuser_ena0 | |||
55:0- tx_preamblein | |||
rx_axis_tvalid_* | 1 | O | Receive AXI4-Stream Data valid. |
rx_axis_tdata_* | 128 | O | Receive AXI4-Stream Data bus. |
rx_axis_tuser | 70 | O | RX segment and packet information signal. rx_axis_tuser_0[69:0] |
69 - rx_axis_tuser_err1 | |||
68:66 - rx_axis_tuser_mty1[2:0] | |||
65 - rx_axis_tuser_eop1 | |||
64 - rx_axis_tuser_sop1 | |||
63 - rx_axis_tuser_ena1 | |||
62 - rx_axis_tuser_err0 | |||
61:59 - rx_axis_tuser_mty0[2:0] | |||
58 - rx_axis_tuser_eop0 | |||
57 - rx_axis_tuser_sop0 | |||
56 - rx_axis_tuser_ena0 | |||
55:0 - rx_preamblein |