1588v2 Port List and Descriptions - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

The following table details the additional signals present when the packet timestamping feature is included.

Table 1. 1588v2 Port List and Descriptions
Signal I/O Description Clock Domain
IEEE 1588 Interface – TX Path
ctl_tx_systemtimerin[80-1:0] I System timer input for the TX. In normal clock mode, the 32 LSBs carry nsec and the 48 MSBs carry seconds. In transparent clock mode, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to IEEE 1588v2 for the representational definitions.

This input must be in the TX SerDes clock domain.

tx_serdes_clk
tx_ptp_tstamp_valid_out O This bit indicates that a valid timestamp is being presented on the TX system interface. tx_clk_out
tx_ptp_tstamp_tag_out[15:0] O Tag output corresponding to tx_ptp_tag_field_in[15:0] tx_clk_out
tx_ptp_tstamp_out[80-1:0] O Time stamp for the transmitted packet SOP corresponding to the time at which it passed the capture plane. Used for 2-step 1588 operation. Time format is the same as timer input. tx_clk_out
tx_ptp_1588op_in[1:0] I

This signal should be valid on the first cycle of the packet and applies to each packet presented on the Transmit AXI4-Stream Interface.

2’b00 – No operation: no timestamp is taken and the frame is not modified.

2’b01 – 1-step: a timestamp is taken and inserted into the frame.

2’b10 – 2-step: a timestamp is taken and returned to the client using the additional ports of 2-step operation. The frame itself is not be modified.

2’b11 – Reserved: act as No operation.

tx_clk_out
ctl_tx_ptp_1step_enable I When set to 1, this bit enables 1-step operation.
Note: This input should only be changed when the corresponding reset input is asserted. It should not be changed dynamically during packet transmission.
tx_clk_out
ctl_ptp_transpclk_mode I When set to 1, this input places the timestamping logic into transparent clock mode. In this mode, the system timer input is interpreted as a correction value. The TX adds the correction value to the TX timestamp according to the process defined in IEEE 1588v2.

It is expected that the corresponding incoming PTP packet correction field has already been adjusted with the proper RX timestamp.

Note: This input should only be changed when the corresponding reset input is asserted. It should not be changed dynamically during packet transmission.
tx_clk_out
rx_ptp_tstamp_valid_out O This bit indicates that a valid time stamp is being presented on the RS system interface.
Note: This is valid for a 256-bit Regular Streaming interface data path only.
tx_ptp_tag_field_in[15:0] I The usage of this field is dependent on the 1588 operation. This signal should be valid on the first cycle of the packet.
  • For No operation, this field is ignored.
  • For 1-step and 2-step this field is a tag field. This tag value is returned to the client with the timestamp for the current frame using the additional ports of 2-step operation. This tag value can be used by software to ensure that the timestamp can be matched with the PTP frame that it sent for transmission.
tx_clk_out
ctl_tx_ptp_latency_adjust[10:0] I This bus can be used to adjust the 1-step TX timestamp with respect to the 2-step timestamp. The units of bits [10:3] are nanoseconds and bits [2:0] are fractional nanoseconds.
Note: This input should only be changed when the corresponding reset input is asserted. It should not be changed dynamically during packet transmission.
tx_clk_out
stat_tx_ptp_fifo_write_error O Transmit PTP FIFO write error. A value of 1 on this status indicates that an error occurred during the PTP Tag write. A TX Path reset is required to clear the error. tx_clk_out
stat_tx_ptp_fifo_read_error O Transmit PTP FIFO read error. A value of 1 on this status indicates that an error occurred during the PTP Tag read. A TX Path reset is required to clear the error. tx_clk_out
IEEE 1588 Interface – RX Path
ctl_rx_systemtimerin[80-1:0] I System timer input for the RX. Same time format as the TX. This input must be in the same clock domain as the RX SerDes. rx_serdes_clk
rx_ptp_tstamp_out[80-1:0] O Time stamp for the received packet SOP corresponding to the time at which it passed the capture plane. The signal is valid on the first cycle of the packet. rx_clk_out
tx_ptp_upd_chksum_in I See tx_ptp_upd_chksum_in in IEEE 1588 TX/RX Interface Control /Status /Statistics Signals.
tx_ptp_pcslane_out O See tx_ptp_pcslane_out in IEEE 1588 TX/RX Interface Control /Status /Statistics Signals.
tx_ptp_chksum_offset_in I See tx_ptp_chksum_offset_in in IEEE 1588 TX/RX Interface Control /Status /Statistics Signals.
rx_ptp_pcslane_out O See rx_ptp_pcslane_out in IEEE 1588 TX/RX Interface Control /Status /Statistics Signals.
rx_lane_aligner_fill O See rx_lane_aligner_fill in IEEE 1588 TX/RX Interface Control /Status /Statistics Signals.