AXI4-Lite Interface Implementation - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

If you want to instantiate the AXI4-Lite interface to access the control and status registers of the l_ethernet core, you must enable the Include AXI4-Lite check box in the Configuration tab. It enables the l_ethernet _0_axi_if_top module (that contains l_ethernet_0_pif_registers with the l_ethernet _0_slave_2_ipif module). You can accesses the AXI4-Lite interface logic registers (control, status and statistics) from the l_ethernet _0_pkt_gen_mon module.

This mode enables the following features:

  • You can configure all the control (CTL) ports of the core through the AXI4-Lite interface. This operation is performed by writing to a set of address locations with the required data to the register map interface.
  • You can access all the status and statistics registers from the core through the AXI4-Lite interface. This is performed by reading the address locations for the status and statistics registers through register map.