AXI4-Stream Interface – 128-bit Straddle Packet Interface - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)
Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

In the AXI4-Stream interface, the following tables describe the clock/reset signals, the Receive interface signals, and the Transmit interface signals.

Table 1. AXI4-Stream Interface – Clock/Reset Signals
Name I/O Description
dclk I This must be a convenient stable clock, for example 75 MHz. Refer to the current transceiver guide for up to date information.
rx_reset I Reset for the RX circuits. This signal is active-High (1 = reset) and must be held High until clk is stable. The 40G/50G High Speed Ethernet Subsystem handles synchronizing the rx_reset input to the appropriate clock domains within the core. This is a synchronous reset.
refclk_n0 I Differential reference clock for the transceiver (N).
refclk_p0 I Differential reference clock for the transceiver (P).
tx_reset I Reset for the TX circuits. This signal is active-High (1 = reset) and must be held High until clk is stable. The 40G/50G High Speed Ethernet Subsystem handles synchronizing the tx_reset input to the appropriate clock domains within the core. This is a synchronous reset.