The Ethernet register map is divided into three sections as follows:
| Address Base | Address Space Name |
|---|---|
| 0x0000 | IP Configuration Registers |
| 0x0400 | Status Registers |
| 0x0500 | Statistics Counters |
All registers are 32 bits in size, and aligned on 32-bit addressing. The registers are designed such that the full 32b register is read/written (Byte write enables are ignored). In the below register space maps, any holes in the address space should be considered RESERVED and can cause an AXI-Ctl interface IP core to respond with an error if accessed.
When the AXI interface counters are selected, a “tick” register (TICK_REG) write/read is used to capture the statistics from the core clock domain on to the AXI clock domain, at the same time clearing the counters. After the “tick” is issued, the counters contain their updated value and can be read multiple times without destruction of this data.
The register reset signal is s_axi_aresetn, which is active-Low. This
reset forces all registers to their default values as indicated in these tables.