Port Name Changes
-
qpll0clk_in
to qpll0_clk_in_*
-
qpll0refclk_in
to qpll0_refclk_in_*
-
qpll1clk_in
to qpll1_clk_in_*
-
qpll1refclk_in
to qpll1_refclk_in_*
-
gtwiz_reset_qpll0lock_in
to
gtwiz_reset_qpll0_lock_in_*
-
gtwiz_reset_qpll0lock_out
to
gtwiz_reset_qpll0_lock_out_*
-
Stat_rx_rsfec_symbol_error_count 0_inc_*
to
Stat_rx_rsfec_error_count 0_inc_*
-
Stat_rx_rsfec_symbol_error_count 1_inc_*
to
Stat_rx_rsfec_error_count 1_inc_*
-
Stat_tx_rsfec_pcs_block_lock_*
to
Stat_tx_rsfec_block_lock_*
Ports Added
-
ctl_tx_ptp_1step_enable_*
-
ctl_tx_ptp_latency_adjust_*
-
ctl_tx_ptp_vlane_adjust_mode_*
-
ctl_ptp_transpclk_mode_*
-
tx_ptp_upd_chksum_in_*
-
tx_ptp_chksum_offset_in_*
-
tx_ptp_rxtstamp_in_*
-
stat_an_rxcdrhold_*
-
gt_drp_done_0
-
ctl_rate_mode_0
-
txpllclksel_in_0
-
rxpllclksel_in_0
-
txsysclksel_in_0
-
rxsysclksel_in_0
-
Rxafecfoken_0
-
Rxdfecfokfcnum_0
-
Speed_0
-
anlt_done_0
-
rxdata_out_0
-
txdata_in_0