Clause 91 RS-FEC Interface Control/Status/Statistics Signals - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)
Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

Ports under this section are available when Clause 91 (RS-FEC) is selected from the Configuration tab.

Table 1. Clause 91 RS-FEC Interface Control/Status/Statistics Signals
Name Size I/O Description
ctl_rsfec_enable_* 1 I Changes only take effect after the reset. New value is sampled on the first cycle after reset. Enable RS-FEC function.
  • 1: Enable RS-FEC
  • 0: Bypass RS-FEC
ctl_rx_rsfec_enable_correction_* 1 I Changes only take effect after the reset. New value is sampled on the first cycle after reset. Equivalent to MDIO register 1.200.0.
  • 0: Decoder performs error detection without error correction (see IEEE 802.3802.3 by section 91.5.3.3)
  • 1: Decoder also performs error correction
ctl_rx_rsfec_enable_indication_* 1 I Changes only take effect after the reset. New value is sampled on the first cycle after reset. Equivalent to MDIO register 1.200.1
  • 0: Bypass the error indication function (see IEEE Std 802.3 by section 91.5.3.3)
  • 1: Decoder indicates errors to the PCS sublayer
ctl_rsfec_ieee_error_indication_mode_* 1 I Changes only take effect after the reset. New value is sampled on the first cycle after reset.
  • 1: Core conforms to the IEEE RS-FEC specification
  • 0: If ctl_rx.rsfec_enable_correction and ctl_rx_rsfec_enable_indication are 0, the RS decoder is bypassed
stat_tx_rsfec_block_lock_* 1 O TX PCS block lock status
  • 0: unlocked
  • 1: locked
stat_tx_rsfec_lane_alignment_status_* 1 O TX PCS frame alignment status
  • 0: unaligned
  • 1: aligned
stat_rx_rsfec_am_lock0 1 O RX lane 1 lock status
  • 0: unlocked
  • 1: locked
stat_rx_rsfec_am_lock1 1 O RX lane 1 lock status
  • 0: unlocked
  • 1: locked
stat_rx_rsfec_lane_alignment_status_* 1 O RX alignment status
  • 0: unaligned
  • 1: aligned
stat_rx_rsfec_lane_fill_0 14 O RX lane 0 additional delay.

The top seven bits [13:7] of each delay bus is the number of additional clock cycles delay being added due to deskew. The bottom seven bits [6:0] of each delay bus is the fractional clock cycle delay being added due to deskew, in units of 1/66th of a clock cycle.
stat_rx_rsfec_lane_fill_1 14 O RX lane 1 additional delay.

The top seven bits [13:7] of each delay bus is the number of additional clock cycles delay being added due to deskew. The bottom seven bits [6:0] of each delay bus is the fractional clock cycle delay being added due to de-skew, in units of 1/66th of a clock cycle.
stat_rx_rsfec_lane_mapping_* 2 O RX lane mapping
  • bit 0: index of FEC lane carried on PMA lane 0
  • bit 1: index of FEC lane carried on PMA lane 1
stat_rx_rsfec_hi_ser_* 1 O This output is only active when the core is in bypass indication mode. It indicates when High that the number of FEC symbol errors in a window of 8192 codewords has exceeded the threshold K (417).
stat_rx_rsfec_corrected_cw_inc_* 1 O Corrected codeword count increment
stat_rx_rsfec_uncorrected_cw_inc_* 1 O Uncorrected codeword count increment
stat_rx_rsfec_error_count0_inc_* 3 O Symbol error count increment for lane 0.
stat_rx_rsfec_error_count1_inc_* 3 O Symbol error count increment for lane 1.