| Name | Size | I/O | Description |
|---|---|---|---|
| sys_reset | 1 | I | Async reset for core This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab. |
| dclk | 1 | I | Stable/free running input clk to the GT This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab. |
| gt_refclk_p | 1 | I | Differential input clk to the GT. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core is selected in the Shared Logic tab. |
| gt_refclk_n | 1 | I | Differential input clk to GT. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core is selected in the Shared Logic tab. |
| qpll0_clk_in_* | 2/4 | I | QPLL0 clock input.(QPPL is quad phase-locked
loop) This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core is selected in the Shared Logic tab. Port width: 2 bits for the 50G single coreand 4 bit for 40G one core and 50G two cores. |
| qpll0_refclk_in_* | 2/4 | I | QPLL0 ref clock input. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core is selected in the Shared Logic tab. Port width: 2 bits for the 50G single coreand 4 bit for 40G one core and 50G two cores. |
| qpll1_clk_in_* | 2/4 | I | QPLL1 clock input. This port is available when the Include GT subcore in core option is selected in the GTSelection and Configuration tab and Include Shared Logic in core is selected in the Shared Logic tab. Port width: 2 bits for the 50G single core and 4 bits for 40G one core and 50G two cores. |
| qpll1_refclk_in_* | 2/4 | I | QPLL1 ref clock input. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and Include Shared Logic in example design is selected in the Shared Logic tab. Port width: 2 bits for the 50G single core and 4 bits for 40G one core and 50G two cores. |
| gtwiz_reset_qpll0_lock_in_* | 1 | I | QPLL0 lock reset input to the GT. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and Include Shared Logic in example design is selected in the Shared Logic tab. |
| gtwiz_reset_qpll0_reset_out_* | 1 | O | QPLL0 lock reset output from the GT. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and Include Shared Logic in example design is selected in the Shared Logic tab. |
| tx_clk_out_* | 1 | O | TX user clock output from GT. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab. |
| rx_serdes_clk_* | 1 | I | RX SerDes clock input to core This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab. The GT type is not GTM. |
| rxrecclkout_* | 1 | O | RX recovered clock output from GT. |
| tx_core_clk_* | 1 | I | TX Core clock input from GT wrapper. This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab. |
| rx_core_clk _* | 1 | I | RX Core clock input to the core. |
| tx_mii_clk_* | 1 | O | TX user clock output from GT. This port is available when the core type is Ethernet MAC+PCS/PMA and the Include GT subcore in core option is selected in the GT Selection and Configuration tab. |
| rx_clk_out_* | 1 | O | RX user clock output from the GT. |
| tx_reset_* | 1 | I | TX reset input to the core. |
| user_tx_reset_* | 1 | O | TX reset output for the user logic. The
user_tx_reset goes high to reset user logic when the clocks become
unstable. This signal is asserted when GT resetdone goes low. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core is selected in the Shared Logic tab. |
| gt_reset_tx_done_out_* | 1 | O |
TX reset done signal from the GT. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core is selected in the Shared Logic tab. |
| rx_reset_* | 1 | I | RX reset input to the core. |
| user_rx_reset_* | 1 | O | RX reset output for the user logic. The
user_rx_reset goes high to reset user logic when the clocks become
unstable. This signal is asserted when GT resetdone goes low. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core is selected in the Shared Logic tab. |
| rsfec_txoutclk_out_* | 1 | I | Stable TX input clock to the Soft KP4 RS-FEC
block. Note: This port is available for GTM devices, when Soft KP4 RS-FEC
option is enabled and Include Shared Logic in Example Design
option is selected in the Shared Logic tab. You have to provide
this clock signal (frequency of 332.03125 MHz) to the KP4 RS-FEC
block.
|
| rsfec_rxoutclk_out_* | 1 | I | Stable RX input clock to the Soft KP4 RS-FEC
block. Note: This port is available for GTM devices, when Soft KP4 RS-FEC
option is enabled and Include Shared Logic in Example Design
option is selected in the Shared Logic tab. You have to provide
this clock signal (frequency of 332.03125 MHz) to the KP4 RS-FEC
Block.
|
| rsfec_tx_locked_* | 1 | I | Stable TX resetdone to the Soft KP4 RS-FEC
block. Note: This port is available for GTM devices, when Soft KP4 RS-FEC
option is enabled and Include Shared Logic in Example Design
option is selected in the Shared Logic tab. You have to provide
this signal to the KP4 RS-FEC block.
|
| rsfec_rx_locked_* | 1 | I | Stable RX Resetdone to the Soft KP4 RS-FEC
block. Note: This port is available for GTM devices, when Soft KP4 RS-FEC
option is enabled and Include Shared Logic in Example Design
option is selected in the Shared Logic tab. You have to provide
this signal to the KP4 RS-FEC block.
|
| gt_reset_rx_done_out_* | 1 | O | RX reset done signal from the GT. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core is selected in the Shared Logic tab. |
| rx_serdes_reset_* | 1 | I | RX SerDes reset signal. This port is available when the Include Shared Logic in example design option is selected in the Shared Logic tab. The GT type is not GTM. |
| ctl_gt_reset_all_* | 1 | O |
gt_reset_all signal from the AXI4-Lite register map. This port is available when Include AXI4-Lite is selected from the Configuration tab and the Include Shared Logic in example design is selected in the Shared Logic tab. |
| gtwiz_reset_all_in_* | 1 | I |
gt_reset_all signal from the user. This port is available when Control and Statistics interface is selected from the Configuration tab. |
| ctl_gt_tx_reset_* | 1 | O | gt_tx_reset signal from the AXI4-Lite register map. This port is available when Include AXI4-Lite is selected from the Configuration tab and the Include Shared Logic in example design is selected the Shared Logic tab. |
| gtwiz_tx_datapath_reset_in_* | 1 | I | gt_tx_reset signal from the user. This port is available when the Control and Statistics interface is selected from the Configuration tab. |
| ctl_gt_rx_reset_* | 1 | O | gt_rx_reset signal from the AXI4-Lite register map. This port is available when Include AXI4-Lite is selected from the Configurationtab and the Include Shared Logic in example design is selected in the Shared Logic tab. |
| gtwiz_rx_datapath_reset_in_* | 1 | I | gt_rx_reset signal from the user. This port is available when Control and Statistics interface is selected from the Configuration tab. |
| gt_reset_all_in_* | 1 | I | gt_reset_all signal from the reset_wrapper of
shared logic wrapper. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and Include Shared Logic in example design is selected in the Shared Logic tab. |
| gt_tx_reset_in_* | 1 | I | gt_tx_reset_insignal from reset_wrapper of
shared logic wrapper. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and Include Shared Logic in example design is selected in the Shared Logic tab. |
| gt_rx_reset_in_* | 1 | I | gt_rx_reset_in signal from reset_wrapper of
shared logic wrapper. This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and Include Shared Logic in example design is selected in the Shared Logic tab. |
| gt_refclk_out | 1 | O | gt_refclk which is same as gt_ref_clk to drive user fabric logic. |
| gtpowergood_out_* | 2/4 | O | Refer to the UltraScale Architecture GTH Transceivers User Guide (UG576) or the UltraScale Architecture GTY Transceivers User Guide (UG578) for the port description. |
| TXOUTCLKSEL_IN_* | 6/12 | I | This port is used to select the clock source for the gtwizard TX output clock. This port is driven with 6'b101101/12'b101101101101 as per preset. |
| RXOUTCLKSEL_IN_* | 6/12 | I | This port is used to select the clock source for the gtwizard RX output clock. This port is driven with 6'b101101/12'b101101101101 as per preset. |
| gtwiz_reset_all_in* | 1 | I | gt_reset_all signal from the user. Note: For Versal devices only. This port is available when
you select Control and Statistics interface from the
Configuration tab.
|
| gtwiz_rx_datapath_reset_in_* | 1 | I | gt_rx_reset signal from the user. Note: For Versal devices only. This port is available when
you select Control and Statistics interface from the
Configuration tab.
|
| gtm_txusrclk_out2_* | 1 | O | TX clock output from the core when the GT is included in the
core. Note: This port is
available when the Include GT subcore in core option is selected
in the GT Selection and Configuration tab and the Include Shared
Logic in example design option is selected in the Shared Logic
tab and GT type is GTM.
|
| gtm_rxusrclk_out2_* | 1 | O | RX clock output from the core when the GT is included in the
core. Note: This port is
available when the Include GT subcore in core option is selected
in the GT Selection and Configuration tab and the Include Shared
Logic in example design option is selected in the Shared Logic
tab and GT type is GTM.
|
| gtm_out_txprgdivresetdone_* | 1 | O | TX reset output from the core when the GT is included in the
core. Note: This port is
available when the Include GT subcore in core option is selected
in the GT Selection and Configuration tab and the Include Shared
Logic in example design option is selected in the Shared Logic
tab and GT type is GTM.
|
| gtm_out_rxprgdivresetdone_* | 1 | O | RX reset output from the core when the GT is included in the
core. Note: This port is
available when the Include GT subcore in core option is selected
in the GT Selection and Configuration tab and the Include Shared
Logic in example design option is selected in the Shared Logic
tab and GT type is GTM.
|
| txoutclk_out_* | 1 | I | TX clock input to the core. Note: This port is
available for GTM devices (non-switching configuration), when
the Include Shared Logic in example design option is selected in
the Shared
Logic tab. You have to provide this
signal (312.5 MHz for 40G and 390.625 MHz for 50G) to the
core.
|
| rxoutclk_out_* | 1 | I | RX clock input to the core. Note: This port is
available for GTM devices (non-switching configuration), when
Include Shared Logic in example design option is selected in the
Shared Logic tab.
You have to provide this frequency (312.5 MHz for 40G and
390.625 MHz for 50G) to the core.
|
| tx_locked_* | 1 | I | TX resetdone input to the core. Note: This port is
available for GTM devices,when Include Shared Logic in example
design option is selected in the Shared
Logic tab. You have to provide this
input to the core as per txoutclk_out_* clock.
|
| rx_locked_* | 1 | I | RX resetdone input to the core. Note: This port is
available for GTM devices,when Include Shared Logic in example
design option is selected in the Shared
Logic tab. You have to provide this
input to the core as per rxoutclk_out_* clock.
|
| txoutclk_out_50 | 1 | I | TX clock input to the core. Note: This port is available for Versal GTM devices (For
switching configuration).
|
| txoutclk_out_40 | 1 | I | TX clock input to the core. Note: This port is available for Versal GTM devices (For
switching configuration).
|
| rxoutclk_out_50 | 1 | I |
Note: This port is available for
Versal GTM devices (For
switching configuration).
|
| rxoutclk_out_40 | 1 | I | RX clock input to the core. Note: This port is available for Versal GTM devices (For
switching configuration).
|