Configuration Registers - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

This section contains descriptions of the configuration registers. In the cases where the features described in the bit fields are not present in the IP core, the bit field reverts to RESERVED. Reserved fields in the configuration registers do not accept any written value, and always return a 0 when read. Registers or bit fields within registers can be accessed for read-write (RW), write-only (WO), or read-only (RO). Default values shown are decimal values and take effect after s_axi_aresetn.

A description of each signal is found in the port list section of this document.