Configuration Tab - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID

PG211

Release Date

2023-11-01

Version

3.3 English

The Configuration tab provides the basic core configuration options.

Default values are pre-populated in all tabs.

Figure 1. Configuration Tab for UltraScale/UltraScale+

Figure 2. Configuration Tab for Versal Adaptive SoC

Table 1. Configuration Options
Option	Values	Default
General
Select Core	Ethernet MAC+PCS/PMA Ethernet PCS/PMA	Ethernet MAC+PCS/PMA
Speed	50G 40G	50G
Number of Cores	1 2	1
Clocking	Synchronous Asynchronous	Asynchronous
Runtime Switchable Mode	0,1	0
Data Path Interface	128-bit Straddled AXI4-Stream ¹ 256-bit Regular AXI4-Stream ² MII³	128-bit Straddled AXI4-Stream
PCS/PMA Options
Base-R Base-KR	Base-R Base-KR	Base-KR
Include FEC Logic
Clause 74 (BASE-KR FEC) ^4,6	0,12 mi	0
Clause 91 (RS-FEC)^5,6	0,1	0
KP4 FEC with Transcode⁷	0,1	0
Soft RS-FEC (544,514)	0,1	0
Auto Negotiation/Link Training Logic
Auto Negotiation/Link Training Logic	None Include AN/LT Logic	None
Control and Statistics Interface
Control and Statistics interface	Control and Status Vectors Include AXI4-Lite	Control and Status Vectors
Include Statistics Counters	0,1⁸	1
Statistics Resource Type	Registers, block RAM⁹	Registers
The 128-bit Straddled AXI4-Stream is visible and option for Ethernet MAC+PCS/PMA with 40G and 50G line rate options. The 256-bit Regular AXI4-Stream is visible and option for Ethernet MAC+PCS/PMA with 40G Line rate only. The MII interface is visible and is the only option for the Ethernet PCS/PMA core. Clause 74 (BASE-KR FEC) logic is not supported for Base-R. Clause 91 (RS-FEC) is not supported for Base-R, 40G speed. Clause 74 (BASE-KR FEC) and Clause 91 (RS-FEC) both can be selected in AMD Vivado™ IDE but during functional operation only one can be enabled at a time using the respective control signals. GTM integrated hard FEC. Only applicable for Devices with GTM (Not applicable for AMD Versal™ adaptive SoC). The Statistics Counters are available in the register map only when you enable the Include Statistics Counters option. Otherwise, the Statistics Counters are not available. Statistics Resource Type block RAM option is supported with Ethernet MAC+PCS/PMA configuration. There is only single core support for Versal adaptive SoC. Multi-core is not supported as the example design has GT outside the core.